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Searched refs:lcd0_ch0_clk_cfg (Results 1 – 4 of 4) sorted by relevance

/u-boot/arch/arm/include/asm/arch-sunxi/
A Dclock_sun4i.h70 u32 lcd0_ch0_clk_cfg; /* 0x118 */ member
A Dclock_sun6i.h87 u32 lcd0_ch0_clk_cfg; /* 0x118 LCD0 CH0 module clock */ member
/u-boot/drivers/video/sunxi/
A Dlcdc.c316 &ccm->lcd0_ch0_clk_cfg); in lcdc_pll_set()
A Dsunxi_display.c536 setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_RST); in sunxi_lcdc_init()
800 setbits_le32(&ccm->lcd0_ch0_clk_cfg, CCM_LCD_CH0_CTRL_TVE_RST);

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