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Searched refs:level0_table (Results 1 – 1 of 1) sorted by relevance

/u-boot/arch/arm/cpu/armv7/ls102xa/
A Dcpu.c152 u32 *level0_table = (u32 *)gd->arch.tlb_addr; in mmu_setup() local
159 set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
160 set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL); in mmu_setup()
162 set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM); in mmu_setup()
164 set_pgtable(level0_table, 0, (u32)level1_table); in mmu_setup()
193 : : "r" ((u32)level0_table), "r" (0) : "memory"); in mmu_setup()

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