| /u-boot/arch/mips/mach-ath79/qca956x/ |
| A D | qca956x-ddr-tap.S | 18 li a0, 0xbd001f00
32 li a3, 0xffffffff
39 li a1, 0x1
42 li a2, 0x2
53 li t2, 0x00000000
68 li t1, 0x0000ffff
71 li t1, 0x0000ffff
74 li t1, 0x0000ffff
95 li t2, 0x1
154 li t2, 0x3f
[all …]
|
| /u-boot/arch/mips/mach-ath79/ar933x/ |
| A D | lowlevel_init.S | 79 li t3, 0x03
95 li t2, 0x20
111 li t1, 0x03
117 li t1, 0x00
122 li t1, 0x01
166 li t1, 0x0352
170 li t1, 0x0550
222 li t3, 100
223 li t4, 0
230 li t3, 5
[all …]
|
| /u-boot/board/imgtec/malta/ |
| A D | lowlevel_init.S | 66 li t0, CPU_TO_GT32(0xdf000000)
120 li t1, 0x0
121 li t2, -CONFIG_SYS_MEM_SIZE
128 li t1, MALTA_MSC01_IP1_BASE
129 li t2, -MALTA_MSC01_IP1_SIZE
136 li t1, MALTA_MSC01_IP2_BASE1
140 li t1, MALTA_MSC01_IP2_BASE2
146 li t1, MALTA_MSC01_IP3_BASE
147 li t2, -MALTA_MSC01_IP3_SIZE
165 li t3, MALTA_MSC01_PCIIO_MAP
[all …]
|
| /u-boot/arch/nds32/include/asm/ |
| A D | macro.h | 25 li $r4, \addr
26 li $r5, \data
31 li $r4, \addr
32 li $r5, \data
37 li $r4, \addr
38 li $r5, \data
48 li $r4, \addr
50 li $r6, \data
56 li $r4, \addr
71 li $r4, \time
|
| /u-boot/arch/nds32/cpu/n1213/ag101/ |
| A D | lowlevel_init.S | 104 li $r0, SMC_BANK0_CR_A
119 li $r2, 0x00151151
124 li $r2, 0x00153153
200 li $r5, 0x0
235 li $r5, AHBC_BSR6_A
267 li $r5, AHBC_BSR6_A
269 li $r4, 0xfff0ffff
271 li $r4, 0x000b0000
279 li $r4, AHBC_BSR4_A
281 li $r6, 0xffffff
[all …]
|
| A D | watchdog.S | 19 li $p0, (CONFIG_FTWDT010_BASE+WD_CR) ! Get the addr of WD CR
22 li $r0, ~WD_ENABLE
|
| /u-boot/arch/mips/mach-ath79/qca953x/ |
| A D | lowlevel_init.S | 103 li t2, 0x08000000
108 li t2, 0xf7ffffff
115 li t1, 0x01
128 li t1, MK_DPLL2(2, 16)
140 li t1, PLL_CPU_CONF_VAL
144 li t1, PLL_DDR_CONF_VAL
148 li t1, PLL_CLK_CTRL_VAL
153 li t2, ~QCA953X_PLL_CONFIG_PWD
159 li t2, ~QCA953X_PLL_CONFIG_PWD
170 li t1, PLL_DDR_DIT_FRAC_VAL
[all …]
|
| /u-boot/arch/mips/mach-mtmips/mt7628/ |
| A D | lowlevel_init.S | 33 li t0, DELAY_USEC(1000000)
34 li t1, KSEG1ADDR(SYSCTL_BASE + SYSCTL_ROM_STATUS_REG)
35 li t2, KSEG1ADDR(SYSCTL_BASE + SYSCTL_CLKCFG0_REG)
74 li a0, 0
75 li a1, CONFIG_SYS_ICACHE_SIZE
85 li a0, 0
86 li a1, CONFIG_SYS_DCACHE_SIZE
104 li a1, CACHE_STACK_SIZE /* D-Cache lock size */
105 li a2, 0x1ffff800 /* Mask of DTagLo[PTagLo] */
137 li t0, (CONFIG_SYS_INIT_SP_ADDR + 15) & (~15)
[all …]
|
| /u-boot/arch/mips/mach-jz47xx/ |
| A D | start.S | 36 li t0, 0x0040FC04
41 li t1, 0x00800000
53 li sp, CONFIG_SPL_STACK
66 li t0, KSEG0
73 li t0, KSEG0
88 li t0, CONF_CM_CACHABLE_NONCOHERENT
|
| /u-boot/arch/mips/mach-mscc/ |
| A D | lowlevel_init_luton.S | 30 li v1, 0x00610400
33 li v1, 0x00610c00
36 li v1, 0x00610800
39 li v1, 0x00610000
53 li v1, ~MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0_CPU_CLK_DIV
|
| A D | lowlevel_init.S | 23 li t0, 0x0fffffff
24 li t1, CONFIG_SYS_TEXT_BASE
|
| /u-boot/arch/nds32/cpu/n1213/ |
| A D | start.S | 115 li $r0, 0x0
123 li $r0, ~0x6
128 li $r0, ~0x3
136 li $r0, 0x4
147 li $r0, ~0x18
154 li $r0, ~0x6000
162 li $r0, 0x1
169 li $r0, 0x2
332 li $t4, 1
367 li $t4, 1
[all …]
|
| /u-boot/arch/mips/lib/ |
| A D | cache_init.S | 55 li \sz, 2
76 li $1, 32
89 li t1, CPHYSADDR(~0)
93 li a0, \mode
168 li t2, 2
177 li t2, 64
184 li R_L2_BYPASSED, 1
210 li t1, 2
221 li t1, 64
405 li t2, GCR_REV_CM3
[all …]
|
| /u-boot/board/qemu-mips/ |
| A D | lowlevel_init.S | 18 li t1, 0x00400000
25 li t1, 0x00000003
32 li t1, 0x00800000
|
| /u-boot/arch/powerpc/cpu/mpc8xx/ |
| A D | start.S | 77 li r3, MSR_KERNEL /* Set ME, RI flags */
138 li r2, 0x0007
160 li r0, (0x2000 / 4)
162 li r0, 0
281 li r22,0
294 li r4,0
429 li r0,__got2_entries@sectoff@l
446 li r0,__fixup_entries@sectoff@l
471 li r0, 0
512 li r8, Alignment - _start + EXC_OFF_SYS_RESET
[all …]
|
| /u-boot/arch/powerpc/cpu/mpc86xx/ |
| A D | cache.S | 75 li r5,CACHE_LINE_SIZE-1
102 li r5,CACHE_LINE_SIZE-1
126 li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
149 li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
164 li r0,4096/CACHE_LINE_SIZE
176 li r5, HID0_ICFI|HID0_ILOCK
194 li r5, 0
212 li r5, HID0_DCFI|HID0_DLOCK
228 li r5, HID0_DCFI|HID0_DLOCK
255 li r5, HID0_DCFI|HID0_DLOCK
[all …]
|
| A D | start.S | 144 li r0, 0
284 li r0, 0
502 li r22,0
515 li r4,0
740 li r0,__got2_entries@sectoff@l
782 li r0, 0
856 li r8,MSR_IP
954 li r3,0x1000
956 li r3,0x0400
966 li r3,0x0080
[all …]
|
| /u-boot/arch/powerpc/cpu/mpc85xx/ |
| A D | release.S | 84 li r4,0x48
97 li r3,0
307 li r11,0
385 li r3,0
386 li r8,1
426 li r8,3
443 li r4,0
444 li r5,0
445 li r6,0
447 li r8,0
[all …]
|
| A D | start.S | 103 li r27,0
111 li r4,0x48
169 li r0,2
359 li r2, 0
418 li r3, 0
614 li r1, 0
1111 li r0,0
1165 li r0,0
1180 li r0,0
1286 li r4,0
[all …]
|
| /u-boot/arch/nds32/cpu/n1213/ae3xx/ |
| A D | lowlevel_init.S | 76 li $r0, CONFIG_FTSDMC021_BASE
85 li $r0, SMC_BANK0_CR_A
91 li $r2, 0x00153153
114 li $r4, 0x00000000
115 li $r5, 0x80000000
|
| /u-boot/scripts/ |
| A D | cleanpatch | 19 my($li) = @_;
25 for ($i = 0; $i < length($li); $i++) {
26 $c = substr($li, $i, 1);
57 my($li) = @_;
62 for ($i = 0; $i < length($li); $i++) {
63 $c = substr($li,$i,1);
|
| /u-boot/arch/riscv/cpu/ |
| A D | start.S | 77 li t0, CONFIG_NR_CPUS
82 li t0, MIE_MSIE
84 li t0, SIE_SSIE
93 li t0, -16
95 li t1, CONFIG_SPL_STACK
97 li t1, CONFIG_SYS_INIT_SP_ADDR
126 li t1, 1
158 li t1, 1
170 li t1, 1
325 li t3, RELOC_TYPE
[all …]
|
| /u-boot/arch/powerpc/cpu/mpc83xx/ |
| A D | start.S | 251 li r0, 0
434 li r22,0
446 li r4,0
506 li r4, 0x556C
508 li r4, -0x55C7
735 li r4, HID0_ICFI|HID0_ILOCK
764 li r5, HID0_DCFI|HID0_DLOCK
776 li r5, HID0_DCE|HID0_DLOCK
880 30: li r3, 0
974 li r0, 0
[all …]
|
| /u-boot/include/net/ |
| A D | sntp.h | 37 uchar li:2; member
39 uchar li:2;
|
| /u-boot/arch/mips/cpu/ |
| A D | start.S | 40 li t9, 15 # UHI exception operation
41 li a0, 0 # Use hard register context
46 li t0, -16
55 li t2, CONFIG_VAL(SYS_MALLOC_F_LEN)
181 li t1, 0x7 # Clear I, R and W conditions
|