| /u-boot/arch/x86/cpu/ivybridge/ |
| A D | cpu.c | 134 struct udevice *dev, *lpc; in checkcpu() local
180 uclass_first_device(UCLASS_LPC, &lpc); in checkcpu()
181 enable_usb_bar(pci_get_controller(lpc->parent)); in checkcpu()
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| A D | Makefile | 10 obj-y += lpc.o
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| /u-boot/doc/device-tree-bindings/misc/ |
| A D | intel-lpc.txt | 8 - compatible = "intel,lpc"
45 lpc {
46 compatible = "intel,lpc";
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| A D | cros-ec.txt | 22 to the EC (e.g. i2c, spi, lpc). The reg property (as usual) will indicate
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| /u-boot/arch/x86/lib/ |
| A D | lpc-uclass.c | 10 UCLASS_DRIVER(lpc) = {
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| A D | Makefile | 23 obj-y += lpc-uclass.o
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| /u-boot/arch/x86/cpu/intel_common/ |
| A D | cpu.c | 42 struct udevice *dev, *lpc; in cpu_common_init() local
64 ret = uclass_first_device(UCLASS_LPC, &lpc); in cpu_common_init()
67 if (!lpc) in cpu_common_init()
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| A D | Makefile | 27 obj-y += lpc.o
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| /u-boot/arch/x86/cpu/apollolake/ |
| A D | Makefile | 24 obj-y += lpc.o
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| A D | cpu_spl.c | 155 struct udevice *pmc, *sa, *p2sb, *serial, *spi, *lpc; in arch_cpu_init_tpl() local
197 ret = uclass_first_device_err(UCLASS_LPC, &lpc); in arch_cpu_init_tpl()
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| /u-boot/drivers/usb/mtu3/ |
| A D | mtu3_gadget_ep0.c | 350 u32 lpc; in ep0_handle_feature_dev() local
369 lpc = mtu3_readl(mbase, U3D_LINK_POWER_CONTROL); in ep0_handle_feature_dev()
371 lpc |= SW_U1_REQUEST_ENABLE; in ep0_handle_feature_dev()
373 lpc &= ~SW_U1_REQUEST_ENABLE; in ep0_handle_feature_dev()
374 mtu3_writel(mbase, U3D_LINK_POWER_CONTROL, lpc); in ep0_handle_feature_dev()
384 lpc = mtu3_readl(mbase, U3D_LINK_POWER_CONTROL); in ep0_handle_feature_dev()
386 lpc |= SW_U2_REQUEST_ENABLE; in ep0_handle_feature_dev()
388 lpc &= ~SW_U2_REQUEST_ENABLE; in ep0_handle_feature_dev()
389 mtu3_writel(mbase, U3D_LINK_POWER_CONTROL, lpc); in ep0_handle_feature_dev()
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| /u-boot/arch/x86/cpu/broadwell/ |
| A D | Makefile | 25 obj-y += lpc.o
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| /u-boot/arch/x86/include/asm/arch-apollolake/acpi/ |
| A D | southbridge.asl | 25 #include <asm/acpi/lpc.asl>
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| /u-boot/arch/arm/dts/ |
| A D | ast2500.dtsi | 280 lpc: lpc@1e789000 { label
281 compatible = "aspeed,ast2500-lpc", "simple-mfd";
288 lpc_bmc: lpc-bmc@0 {
289 compatible = "aspeed,ast2500-lpc-bmc";
293 lpc_host: lpc-host@80 {
294 compatible = "aspeed,ast2500-lpc-host", "simple-mfd", "syscon";
302 lpc_ctrl: lpc-ctrl@0 {
303 compatible = "aspeed,ast2500-lpc-ctrl";
308 lpc_snoop: lpc-snoop@0 {
309 compatible = "aspeed,ast2500-lpc-snoop";
[all …]
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| A D | stih407-clock.dtsi | 165 "clk-dss-lpc",
318 "clk-lpc-0",
319 "clk-lpc-1";
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| A D | stih410-clock.dtsi | 166 "clk-dss-lpc",
328 "clk-lpc-0",
329 "clk-lpc-1";
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| A D | stih407-family.dtsi | 7 #include <dt-bindings/mfd/st-lpc.h>
601 lpc@8787000 {
602 compatible = "st,stih407-lpc";
608 st,lpc-mode = <ST_LPC_MODE_WDT>;
611 lpc@8788000 {
612 compatible = "st,stih407-lpc";
616 st,lpc-mode = <ST_LPC_MODE_CLKSRC>;
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| A D | ast2600.dtsi | 494 lpc: lpc@1e789000 { label
495 compatible = "aspeed,ast2600-lpc", "simple-mfd", "syscon";
537 lpc_ctrl: lpc-ctrl@80 {
538 compatible = "aspeed,ast2600-lpc-ctrl";
543 lpc_snoop: lpc-snoop@80 {
544 compatible = "aspeed,ast2600-lpc-snoop";
556 compatible = "aspeed,ast2600-lpc-reset";
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| /u-boot/arch/x86/dts/ |
| A D | chromebook_samus.dts | 635 lpc {
636 compatible = "intel,broadwell-lpc";
643 compatible = "google,cros-ec-lpc";
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| A D | chromebook_link.dts | 471 lpc {
472 compatible = "intel,bd82x6x-lpc";
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| A D | chromebook_coral.dts | 97 u-boot,acpi-dsdt-order = <&board &lpc>;
591 lpc: lpc { label
592 compatible = "intel,apl-lpc";
599 compatible = "google,cros-ec-lpc";
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| /u-boot/arch/x86/include/asm/arch-baytrail/acpi/ |
| A D | lpc.asl | 7 * Modified from coreboot src/soc/intel/baytrail/acpi/lpc.asl
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| A D | southcluster.asl | 200 #include "lpc.asl"
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| /u-boot/arch/x86/include/asm/arch-quark/acpi/ |
| A D | southcluster.asl | 179 #include "lpc.asl"
|