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Searched refs:lw (Results 1 – 17 of 17) sorted by relevance

/u-boot/arch/mips/mach-ath79/qca956x/
A Dqca956x-ddr-tap.S45 lw a1, 0x0044(a0) /* RTC_SYNC_STATUS_ADDRESS */
52 lw t1, 0x0(t0)
98 lw t1, 0x0120(t0) /* DDR_BIST_STATUS_ADDRESS */
125 lw t1, 0x4(t0)
130 lw t1, 0x0(t0)
136 lw t1, 0x0(t0)
145 lw t1, 0x0(t0)
153 lw t1, 0x0(t0)
166 lw t1, 0x4(t0)
176 lw t1, 0x0(t0)
[all …]
/u-boot/arch/mips/mach-ath79/ar933x/
A Dlowlevel_init.S82 lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
86 lw t1, AR933X_RESET_REG_RESET_MODULE(t0)
100 lw t5, AR933X_RESET_REG_BOOTSTRAP(t0)
129 lw t1, AR933X_RTC_REG_STATUS(t0)
148 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
189 lw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
215 lw t1, AR933X_PLL_CPU_CONFIG_REG(t0)
234 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
254 lw t1, AR933X_SRIF_DDR_DPLL4_REG(t0)
259 lw t1, AR933X_SRIF_DDR_DPLL3_REG(t0)
/u-boot/board/imgtec/boston/
A Dlowlevel_init.S29 1: lw t1, 0(t0)
47 lw k1, 0(a0)
49 lw k1, 4(a0)
/u-boot/arch/mips/mach-mscc/
A Dlowlevel_init_luton.S24 lw v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0
43 2: lw v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0
50 1: lw v0, MACRO_CTRL_PLL5G_CFG_PLL5G_CFG0
/u-boot/arch/mips/mach-ath79/qca953x/
A Dlowlevel_init.S102 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
107 lw t1, QCA953X_RESET_REG_RESET_MODULE(t0)
122 lw t1, QCA953X_RTC_REG_SYNC_STATUS(t0)
135 lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
152 lw t1, QCA953X_PLL_CPU_CONFIG_REG(t0)
158 lw t1, QCA953X_PLL_DDR_CONFIG_REG(t0)
164 lw t1, QCA953X_PLL_CLK_CTRL_REG(t0)
/u-boot/arch/mips/mach-mtmips/mt7628/
A Dlowlevel_init.S38 lw t3, 0(t1)
45 lw t3, 0(t2)
52 lw t3, 0(t2)
61 lw t3, 0(t2)
/u-boot/arch/mips/include/asm/
A Dasm.h142 #define REG_L lw
163 #define INT_L lw
200 #define LONG_L lw
249 #define PTR_L lw
/u-boot/drivers/video/
A Dbus_vcxk.c366 unsigned long lw; in vcxk_display_bitmap() local
391 lw = (((width + 7) / 8) + 3) & ~0x3; in vcxk_display_bitmap()
394 dataptr = dataptr + lw * (height - c_height); in vcxk_display_bitmap()
397 vcxk_draw_mono(dataptr, lw, c_width, c_height); in vcxk_display_bitmap()
/u-boot/board/imgtec/malta/
A Dlowlevel_init.S32 lw t0, 0(t0)
110 lw t1, MSC01_PBC_CS0CFG_OFS(t0)
223 lw t1, MSC01_PCI_CFG_OFS(t0)
/u-boot/arch/riscv/include/asm/
A Dasm.h23 #define REG_L __REG_SEL(ld, lw)
/u-boot/arch/mips/mach-jz47xx/
A Dstart.S47 lw t1, 0x24(t0)
/u-boot/arch/riscv/lib/
A Dsetjmp.S14 #define LOAD_IDX(reg, idx) lw reg, (idx*4)(a0)
A Dcrt0_riscv_efi.S22 #define LOAD_LONG(reg, idx) lw reg, (idx*SIZE_LONG)(sp)
/u-boot/arch/mips/lib/
A Dcache_init.S162 lw t1, GCR_L2_CONFIG(t0)
371 lw t1, GCR_L2_CONFIG(t0)
404 lw t1, GCR_REV(t0)
/u-boot/arch/microblaze/cpu/
A Dstart.S277 1: lw r12, r21, r5 /* Load u-boot data */
303 3: lw r12, r21, r0 /* Load entry */
/u-boot/arch/riscv/cpu/
A Dmtrap.S18 #define LREG lw
A Dstart.S20 #define LREG lw

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