| /u-boot/post/lib_powerpc/fpu/ |
| A D | 20010226-1.c | 22 volatile long double m2; in fpu_post_test_math3() local
26 m2 = m1 * 4294967296.0; in fpu_post_test_math3()
27 mant_long = ((unsigned long) m2) & 0xffffffff; in fpu_post_test_math3()
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| /u-boot/arch/arm/dts/ |
| A D | sun50i-h5-bananapi-m2-plus.dts | 6 #include <sunxi-bananapi-m2-plus.dtsi>
10 compatible = "sinovoip,bpi-m2-plus", "allwinner,sun50i-h5";
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| A D | sun50i-h5-bananapi-m2-plus-v1.2.dts | 6 #include <arm/sunxi-bananapi-m2-plus-v1.2.dtsi>
10 compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun50i-h5";
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| A D | sun8i-h3-bananapi-m2-plus-v1.2.dts | 8 #include "sunxi-bananapi-m2-plus-v1.2.dtsi"
12 compatible = "bananapi,bpi-m2-plus-v1.2", "allwinner,sun8i-h3";
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| A D | sun8i-h2-plus-bananapi-m2-zero.dts | 5 * Based on sun8i-h3-bananapi-m2-plus.dts, which is:
18 compatible = "sinovoip,bpi-m2-zero", "allwinner,sun8i-h2-plus";
33 label = "bananapi-m2-zero:red:pwr";
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| A D | sunxi-bananapi-m2-plus-v1.2.dtsi | 6 #include "sunxi-bananapi-m2-plus.dtsi"
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| A D | sun8i-h3-bananapi-m2-plus.dts | 45 #include "sunxi-bananapi-m2-plus.dtsi"
49 compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
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| A D | sun6i-a31s-sinovoip-bpi-m2.dts | 49 compatible = "sinovoip,bpi-m2", "allwinner,sun6i-a31s";
65 label = "bpi-m2:blue:usr";
70 label = "bpi-m2:green:usr";
75 label = "bpi-m2:red:usr";
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| /u-boot/arch/arm/include/asm/arch-omap3/ |
| A D | clock.h | 35 unsigned int m2; member
42 unsigned int m2; member
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| /u-boot/arch/arm/mach-omap2/omap3/ |
| A D | clock.c | 152 0xF8000000, ptr->m2 << 27); in dpll3_init_34xx()
206 clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27); in dpll3_init_34xx()
265 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2); in dpll4_init_34xx()
295 clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2); in dpll5_init_34xx()
319 0x0000001F, ptr->m2); in mpu_init_34xx()
350 0x0000001F, ptr->m2); in iva_init_34xx()
402 0xF8000000, ptr->m2 << 27); in dpll3_init_36xx()
456 clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27); in dpll3_init_36xx()
507 clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2); in dpll4_init_36xx()
535 clrsetbits_le32(&prcm_base->clksel5_pll, 0x0000001F, ptr->m2); in dpll5_init_36xx()
[all …]
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| /u-boot/configs/ |
| A D | bananapi_m2_zero_defconfig | 7 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h2-plus-bananapi-m2-zero"
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| A D | bananapi_m2_plus_h3_defconfig | 8 CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-bananapi-m2-plus"
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| A D | bananapi_m2_plus_h5_defconfig | 8 CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-bananapi-m2-plus"
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| A D | Sinovoip_BPI_M2_defconfig | 8 CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31s-sinovoip-bpi-m2"
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| A D | bananapi_m2_berry_defconfig | 8 CONFIG_DEFAULT_DEVICE_TREE="sun8i-v40-bananapi-m2-berry"
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| A D | Bananapi_M2_Ultra_defconfig | 11 CONFIG_DEFAULT_DEVICE_TREE="sun8i-r40-bananapi-m2-ultra"
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| /u-boot/scripts/dtc/ |
| A D | data.c | 157 struct marker *m2 = d2.markers; in data_merge() local
159 d = data_append_markers(data_append_data(d1, d2.val, d2.len), m2); in data_merge()
162 for_each_marker(m2) in data_merge()
163 m2->offset += d1.len; in data_merge()
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| /u-boot/arch/xtensa/include/asm/arch-de212/ |
| A D | tie.h | 74 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
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| /u-boot/arch/xtensa/include/asm/arch-dc233c/ |
| A D | tie.h | 97 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
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| /u-boot/arch/xtensa/include/asm/arch-dc232b/ |
| A D | tie.h | 96 XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
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| /u-boot/arch/arm/mach-omap2/am33xx/ |
| A D | clock.c | 24 if (params->m2 >= 0) in setup_post_dividers()
25 writel(params->m2, dpll_regs->cm_div_m2_dpll); in setup_post_dividers()
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| A D | clock_ti814x.c | 224 static void pll_config(u32 base, u32 n, u32 m, u32 m2, in pll_config() argument
231 m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n; in pll_config()
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| /u-boot/arch/arm/include/asm/arch-am33xx/ |
| A D | clock.h | 84 s8 m2; member
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| /u-boot/board/eets/pdu001/ |
| A D | README | 15 manufactured by EETS GmbH (https://www.eets.ch). The core of the board is a m2
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| /u-boot/arch/arm/mach-omap2/ |
| A D | clocks-common.c | 81 if (params->m2 >= 0) in setup_post_dividers()
82 writel(params->m2, &dpll_regs->cm_div_m2_dpll); in setup_post_dividers()
300 ddr_clk = ddr_clk / divider / core_dpll_params->m2; in omap_ddr_clk()
755 freq_config1 |= (core_dpll_params->m2 << in freq_update_core()
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