Home
last modified time | relevance | path

Searched refs:main_pll_pllc1 (Results 1 – 4 of 4) sorted by relevance

/u-boot/arch/arm/mach-socfpga/include/mach/
A Dclock_manager_s10.h37 u32 main_pll_pllc1; member
/u-boot/drivers/clk/altera/
A Dclk-agilex.h33 u32 main_pll_pllc1; member
A Dclk-agilex.c273 CM_REG_WRITEL(plat, cfg->main_pll_pllc1, CLKMGR_MAINPLL_PLLC1); in clk_basic_init()
/u-boot/arch/arm/mach-socfpga/
A Dclock_manager_s10.c74 writel(cfg->main_pll_pllc1, in cm_basic_init()

Completed in 7 milliseconds