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Searched refs:main_pll_pllglob (Results 1 – 4 of 4) sorted by relevance

/u-boot/arch/arm/mach-socfpga/include/mach/
A Dclock_manager_s10.h34 u32 main_pll_pllglob; member
/u-boot/arch/arm/mach-socfpga/
A Dclock_manager_s10.c56 refclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & in cm_basic_init()
65 writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK & in cm_basic_init()
/u-boot/drivers/clk/altera/
A Dclk-agilex.h30 u32 main_pll_pllglob; member
A Dclk-agilex.c267 vcocalib = calc_vocalib_pll(cfg->main_pll_pllm, cfg->main_pll_pllglob); in clk_basic_init()
268 CM_REG_WRITEL(plat, cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_RST_MASK, in clk_basic_init()

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