Searched refs:mbar_writeLong (Results 1 – 6 of 6) sorted by relevance
| /u-boot/board/freescale/m5249evb/ |
| A D | m5249evb.c | 71 mbar_writeLong(MCFSIM_DACR0, 0x00003324); in dram_init()
74 mbar_writeLong(MCFSIM_DMR0, 0x01fc0001); in dram_init()
77 mbar_writeLong(MCFSIM_DACR0, 0x0000332c); /* Set DACR0[IP] (bit 3) */ in dram_init()
82 mbar_writeLong(MCFSIM_DACR0, 0x0000b324); /* Enable the refresh bit, DACR0[RE] (bit 15) */ in dram_init()
86 mbar_writeLong(MCFSIM_DACR0, 0x0000b364); /* Enable DACR0[IMRS] (bit 6); RE remains enabled */ in dram_init()
|
| /u-boot/board/freescale/m5253demo/ |
| A D | m5253demo.c | 46 mbar_writeLong(MCFSIM_DACR0, 0x00003224); in dram_init()
52 mbar_writeLong(MCFSIM_DMR0, temp | 1); in dram_init()
55 mbar_writeLong(MCFSIM_DACR0, 0x0000322c); in dram_init()
65 mbar_writeLong(MCFSIM_DACR0, in dram_init()
73 mbar_writeLong(MCFSIM_DACR0, in dram_init()
|
| /u-boot/arch/m68k/cpu/mcf52x2/ |
| A D | interrupts.c | 89 mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); in dtimer_intr_setup()
|
| A D | cpu_init.c | 267 mbar_writeLong(MCF_FMPLL_SYNCR, CONFIG_SYS_MCF_SYNCR); in cpu_init_f()
270 mbar_writeLong(MCF_FMPLL_SYNCR, in cpu_init_f()
699 mbar_writeLong(MCFSIM_IMR, 0xfffffbff); in cpu_init_f()
|
| /u-boot/arch/m68k/include/asm/ |
| A D | m5249.h | 18 #define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y macro
|
| A D | m5271.h | 17 #define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y macro
|
Completed in 7 milliseconds