| /u-boot/drivers/mtd/nand/raw/ |
| A D | nand_bbt.c | 404 if (md && (md->options & NAND_BBT_VERSION)) { in read_abs_bbts()
407 md->version[0] = buf[bbt_get_ver_offs(mtd, md)]; in read_abs_bbts()
409 md->pages[0], md->version[0]); in read_abs_bbts()
604 if (md) in search_read_bbts()
690 if (!md || md->pages[chip] != page) in write_bbt()
862 if (md) { in check_create()
902 if (md) in check_create()
934 if (md) { in check_create()
1130 if (md) in nand_scan_bbt()
1178 if (md) in nand_update_bbt()
[all …]
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| /u-boot/arch/arm/mach-at91/ |
| A D | mpddrc.c | 53 ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2; in ddr2_init()
56 writel(mpddr_value->md, &mpddr->md); in ddr2_init()
161 ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2; in ddr3_init()
164 writel(mpddr_value->md, &mpddr->md); in ddr3_init()
246 writel(mpddr_value->md, &mpddr->md); in lpddr2_init()
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| /u-boot/drivers/clk/renesas/ |
| A D | r8a77970-cpg-mssr.c | 166 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ argument
167 (((md) & BIT(13)) >> 12) | \
168 (((md) & BIT(19)) >> 19))
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| A D | r8a7792-cpg-mssr.c | 174 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ argument
175 (((md) & BIT(13)) >> 12) | \
176 (((md) & BIT(19)) >> 19))
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| A D | r8a77965-cpg-mssr.c | 280 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ argument
281 (((md) & BIT(13)) >> 11) | \
282 (((md) & BIT(19)) >> 18) | \
283 (((md) & BIT(17)) >> 17))
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| A D | r8a774a1-cpg-mssr.c | 268 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ argument
269 (((md) & BIT(13)) >> 11) | \
270 (((md) & BIT(19)) >> 18) | \
271 (((md) & BIT(17)) >> 17))
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| A D | r8a774b1-cpg-mssr.c | 259 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ argument
260 (((md) & BIT(13)) >> 11) | \
261 (((md) & BIT(19)) >> 18) | \
262 (((md) & BIT(17)) >> 17))
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| A D | r8a7796-cpg-mssr.c | 282 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ argument
283 (((md) & BIT(13)) >> 11) | \
284 (((md) & BIT(19)) >> 18) | \
285 (((md) & BIT(17)) >> 17))
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| A D | r8a774e1-cpg-mssr.c | 281 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ argument
282 (((md) & BIT(13)) >> 11) | \
283 (((md) & BIT(19)) >> 18) | \
284 (((md) & BIT(17)) >> 17))
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| A D | r8a7791-cpg-mssr.c | 232 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ argument
233 (((md) & BIT(13)) >> 12) | \
234 (((md) & BIT(19)) >> 19))
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| A D | r8a7795-cpg-mssr.c | 304 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \ argument
305 (((md) & BIT(13)) >> 11) | \
306 (((md) & BIT(19)) >> 18) | \
307 (((md) & BIT(17)) >> 17))
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| A D | r8a7790-cpg-mssr.c | 230 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ argument
231 (((md) & BIT(13)) >> 12) | \
232 (((md) & BIT(19)) >> 19))
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| A D | r8a77980-cpg-mssr.c | 194 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ argument
195 (((md) & BIT(13)) >> 13))
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| A D | r8a7794-cpg-mssr.c | 206 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \ argument
207 (((md) & BIT(13)) >> 13))
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| A D | r8a77995-cpg-mssr.c | 196 #define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19) argument
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| /u-boot/doc/SPI/ |
| A D | README.ti_qspi_am43x_test | 26 U-Boot# md 0x82000000
43 U-Boot# md 0x82010000
60 U-Boot# md 0x82030000
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| A D | README.ftssp010_spi_test | 25 => md 0x10800000
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| /u-boot/board/st/common/ |
| A D | MAINTAINERS | 3 L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
|
| /u-boot/board/st/stm32mp1/ |
| A D | MAINTAINERS | 3 L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
|
| /u-boot/doc/usage/ |
| A D | base.rst | 17 commands *cmp, cp, md, mdc, mm, ms, mw, mwc*.
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| /u-boot/arch/arm/mach-at91/include/mach/ |
| A D | atmel_mpddrc.h | 20 u32 md; member
39 u32 md; /* 0x20: Memory Device Register */ member
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| /u-boot/board/sbc8641d/ |
| A D | README | 43 d) use "md fff00000" to confirm you are looking at the failed image
48 i) ensure new image is written: "md fff00000"
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| /u-boot/board/sbc8548/ |
| A D | README | 115 md 200000 10
119 md fffa0000 10
122 The "md" steps in the above are just a precautionary step that allow
134 md 200000 10
138 md eff00000 10
146 md 200000 10
150 md fff00000 10
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| /u-boot/board/atmel/sama5d27_som1_ek/ |
| A D | sama5d27_som1_ek.c | 107 ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddrc_conf()
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| /u-boot/board/gardena/smart-gateway-at91sam/ |
| A D | spl.c | 82 ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); in ddr2_conf()
|