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/u-boot/doc/device-tree-bindings/reserved-memory/
A Dreserved-memory.txt1 *** Reserved memory regions ***
3 Reserved memory is specified as a node under the /reserved-memory node.
6 normal use) memory regions. Such memory regions are usually designed for
12 /reserved-memory node
19 /reserved-memory/ child nodes
74 Device node references to reserved memory
79 memory-region (optional) - phandle, specifier pairs to children of /reserved-memory
92 memory {
96 reserved-memory {
115 compatible = "acme,multimedia-memory";
[all …]
/u-boot/arch/arm/dts/
A Dr8a77950-ulcb.dts17 memory@48000000 {
18 device_type = "memory";
23 memory@500000000 {
24 device_type = "memory";
28 memory@600000000 {
29 device_type = "memory";
33 memory@700000000 {
34 device_type = "memory";
A Dk3-j721e-som-p0.dtsi11 memory@80000000 {
12 device_type = "memory";
18 reserved_memory: reserved-memory {
35 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
101 c66_1_dma_memory_region: c66-dma-memory@a6000000 {
107 c66_0_memory_region: c66-memory@a6100000 {
119 c66_1_memory_region: c66-memory@a7100000 {
131 c71_0_memory_region: c71-memory@a8100000 {
353 memory-region = <&c66_0_dma_memory_region>,
359 memory-region = <&c66_1_dma_memory_region>,
[all …]
A Dr8a77950-salvator-x.dts16 memory@48000000 {
17 device_type = "memory";
22 memory@500000000 {
23 device_type = "memory";
27 memory@600000000 {
28 device_type = "memory";
32 memory@700000000 {
33 device_type = "memory";
A Dskeleton.dtsi3 * add a compatible value. The bootloader will typically populate the memory
12 memory { device_type = "memory"; reg = <0 0>; };
A Dr8a774a1-hihope-rzg2m.dts16 memory@48000000 {
17 device_type = "memory";
22 memory@600000000 {
23 device_type = "memory";
A Dskeleton64.dtsi4 * bootloader will typically populate the memory node.
12 memory { device_type = "memory"; reg = <0 0 0 0>; };
A Dsocfpga_cyclone5_mcv.dtsi12 memory@0 {
13 name = "memory";
14 device_type = "memory";
A Dr8a77960-ulcb.dts17 memory@48000000 {
18 device_type = "memory";
23 memory@600000000 {
24 device_type = "memory";
A Ds700-cubieboard7.dts22 memory@0 {
23 device_type = "memory";
27 memory@1,e0000000 {
28 device_type = "memory";
A Dr8a77960-salvator-x.dts16 memory@48000000 {
17 device_type = "memory";
22 memory@600000000 {
23 device_type = "memory";
/u-boot/board/sipeed/maix/
A Dmaix.c21 ofnode memory; in board_init() local
25 memory = ofnode_by_compatible(ofnode_null(), "kendryte,k210-sram"); in board_init()
26 if (ofnode_equal(memory, ofnode_null())) in board_init()
30 ret = clk_get_by_name_nodev(memory, banks[i], &clk); in board_init()
/u-boot/doc/device-tree-bindings/memory-controllers/
A Dst,stm32-fmc.txt1 ST, stm32 flexible memory controller Drive
6 u-boot,dm-pre-reloc: flag to initialize memory before relocation.
8 on-board sdram memory attributes:
12 memory width
13 number of intenal banks in memory
27 include/dt-bindings/memory/stm32-sdram.h to define sdram control and timing
43 /* sdram memory configuration from sdram datasheet */
51 /* sdram memory configuration from sdram datasheet */
/u-boot/arch/powerpc/dts/
A Dqoriq-sec5.0-0.dtsi54 compatible = "fsl,sec-v5.0-rtic-memory",
55 "fsl,sec-v4.0-rtic-memory";
60 compatible = "fsl,sec-v5.0-rtic-memory",
61 "fsl,sec-v4.0-rtic-memory";
66 compatible = "fsl,sec-v5.0-rtic-memory",
67 "fsl,sec-v4.0-rtic-memory";
72 compatible = "fsl,sec-v5.0-rtic-memory",
73 "fsl,sec-v4.0-rtic-memory";
/u-boot/doc/device-tree-bindings/clock/
A Drockchip,rk3368-dmc.txt1 RK3368 dynamic memory controller driver
4 The RK3368 DMC (dynamic memory controller) driver supports setup/initialisation
7 (a) a target-frequency (i.e. operating point) for the memory operation
9 (c) a memory-schedule (i.e. mapping from physical addresses to the address
10 pins of the memory bus)
44 - rockchip,memory-schedule:
54 #include <dt-bindings/memory/rk3368-dmc.h>
66 rockchip,memory-schedule = <DMC_MSCH_CBRD>;
/u-boot/doc/device-tree-bindings/memory/
A Dmemory.txt3 The memory binding for U-Boot is as in the ePAPR with the following additions:
5 Optional subnodes can be used defining the memory layout for different board
11 If subnodes are present, then the /memory node must define these properties:
19 memory-banks - list of memory banks in the same format as normal
37 memory {
65 * Default of 2GB of memory, auto-sized, so could be smaller
66 * 3.5GB of memory (with no auto-size) if (board id & 2) is 2
67 * 1GB of memory (with no auto-size) if board id is 17.
/u-boot/arch/x86/dts/
A Dskeleton.dtsi3 * add a compatible value. The bootloader will typically populate the memory
12 memory { device_type = "memory"; reg = <0 0>; };
/u-boot/arch/mips/dts/
A Dskeleton.dtsi4 * add a compatible value. The bootloader will typically populate the memory
18 memory {
19 device_type = "memory";
/u-boot/lib/
A Dlmb.c22 printf(" memory.cnt = 0x%lx\n", lmb->memory.cnt); in lmb_dump_all_force()
24 (unsigned long long)lmb->memory.size); in lmb_dump_all_force()
25 for (i = 0; i < lmb->memory.cnt; i++) { in lmb_dump_all_force()
102 lmb->memory.cnt = 0; in lmb_init()
103 lmb->memory.size = 0; in lmb_init()
216 struct lmb_region *_rgn = &(lmb->memory); in lmb_add()
321 for (i = lmb->memory.cnt - 1; i >= 0; i--) { in __lmb_alloc_base()
372 lmb->memory.region[rgn].size, in lmb_alloc_addr()
389 rgn = lmb_overlaps_region(&lmb->memory, addr, 1); in lmb_get_free_size()
403 return lmb->memory.region[lmb->memory.cnt - 1].base + in lmb_get_free_size()
[all …]
/u-boot/doc/
A DREADME.memory-test2 hardware, or when using a sloppy port on some board, is memory errors.
4 incorrect initialization of the memory controller. So it appears to
5 be a good idea to always test if the memory is working correctly,
8 U-Boot implements 3 different approaches to perform memory tests:
14 memory banks on this piece of hardware. The code is supposed to be
17 catch 99% of hardware related (i. e. reliably reproducible) memory
23 This is probably the best known memory test utility in U-Boot.
35 no knowledge about memory ranges that may be in use for other
46 system memory) and for U-Boot (code, data, etc. - see above;
69 It should pointed out that _all_ these memory tests have one
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A DREADME.unaligned-memory-access.txt8 when it comes to memory access. This document presents some details about
19 reading 4 bytes of data from address 0x10005 would be an unaligned memory
22 The above may seem a little vague, as memory access can happen in different
24 or write a number of bytes to or from memory (e.g. movb, movw, movl in x86
34 When accessing N bytes of memory, the base memory address must be evenly
41 of memory access. However, we must consider ALL supported architectures;
53 - Some architectures are able to perform unaligned memory accesses
66 memory accesses to happen, your code will not work correctly on certain
75 memory addresses of certain variables, etc.
164 2 bytes (16 bits) to be read from memory starting at address addr1.
[all …]
/u-boot/drivers/w1-eeprom/
A DKconfig25 Maxim DS2502 1-Wire add-only memory support.
26 This device has 128 bytes of data memory, organized as 4 pages of
31 The device may be seen as a 32 byte memory, using the page redirection
32 or as a 128 byte memory, ignoring the page redirection.
38 Sandbox driver for a onewire EEPROM memory
/u-boot/arch/arc/dts/
A Dskeleton.dtsi3 * add a compatible value. The bootloader will typically populate the memory
26 memory@80000000 {
27 device_type = "memory";
/u-boot/drivers/video/stm32/
A DKconfig26 int "Maximum horizontal resolution (for memory allocation purposes)"
31 This configuration is used for reserving/allocating memory for the
35 int "Maximum vertical resolution (for memory allocation purposes)"
40 This configuration is used for reserving/allocating memory for the
44 int "Maximum bits per pixel (for memory allocation purposes)"
49 This configuration is used for reserving/allocating memory for the
/u-boot/arch/arm/mach-versal/
A DKconfig46 bool "Reserve memory for MMU Table"
53 bool "Define TCM and OCM memory in MMU Table"
56 This option if enabled defines the TCM and OCM memory and its
57 memory attributes in MMU table entry.
63 access to DDR memory where DDR is not present.

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