| /u-boot/arch/powerpc/lib/ |
| A D | bat_rw.c | 130 l = mfspr (DBAT0L); in read_bat()
131 u = mfspr (DBAT0U); in read_bat()
134 l = mfspr (IBAT0L); in read_bat()
135 u = mfspr (IBAT0U); in read_bat()
138 l = mfspr (DBAT1L); in read_bat()
139 u = mfspr (DBAT1U); in read_bat()
142 l = mfspr (IBAT1L); in read_bat()
143 u = mfspr (IBAT1U); in read_bat()
146 l = mfspr (DBAT2L); in read_bat()
147 u = mfspr (DBAT2U); in read_bat()
[all …]
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| /u-boot/arch/powerpc/cpu/mpc86xx/ |
| A D | release.S | 30 mfspr r0, MSSCR0
58 mfspr r0, HID0
75 mfspr r3, l2cr
79 mfspr r3, l2cr
88 1: mfspr r3, l2cr
93 mfspr r3, l2cr
100 mfspr r3, HID0
119 mfspr r3, HID0
130 mfspr r4, HID0
137 mfspr r4, HID1
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| A D | cache.S | 36 mfspr r3,HID0
46 mfspr r3,HID0
175 mfspr r3, HID0
193 mfspr r3, HID0
205 mfspr r3, HID0
211 mfspr r3, HID0
227 mfspr r3, HID0
254 mfspr r3, HID0
272 mfspr r3, HID0
280 mfspr r3, l2cr
[all …]
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| A D | start.S | 87 mfspr r4,DAR
89 mfspr r5,DSISR
866 mfspr r0, HID0
917 mfspr r0, HID0
926 mfspr r0, LDSTCR
953 mfspr r0, HID0
965 mfspr r0, LDSTCR
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| A D | cpu.c | 45 uint msscr0 = mfspr(MSSCR0); in checkcpu()
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| A D | traps.c | 119 printf("MSS error. MSSSR0: %08x\n", mfspr(SPRN_MSSSR0)); in MachineCheckException()
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| /u-boot/arch/powerpc/cpu/mpc85xx/ |
| A D | release.S | 32 mfspr r3, SPRN_HDBCR0
48 mfspr r0,PVR
59 mfspr r3,SPRN_HDBCR1
65 mfspr r3,SPRN_SVR
83 mfspr r3,SPRN_HDBCR0
144 mfspr r0,SPRN_PIR
194 mfspr r8, L1CSR2
232 mfspr r3,L1CSR2
244 mfspr r3,L1CSR2
255 mfspr r3,SPRN_SVR
[all …]
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| A D | tlb.c | 54 _mas1 = mfspr(MAS1); in read_tlbcam_entry()
58 *epn = mfspr(MAS2) & MAS2_EPN; in read_tlbcam_entry()
59 *rpn = mfspr(MAS3) & MAS3_RPN; in read_tlbcam_entry()
61 *rpn |= ((u64)mfspr(MAS7)) << 32; in read_tlbcam_entry()
68 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; in print_tlbcam()
104 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; in init_used_tlb_cams()
113 if (mfspr(MAS1) & MAS1_VALID) in init_used_tlb_cams()
209 _mas0 = mfspr(MAS0); in find_tlb_idx()
210 _mas1 = mfspr(MAS1); in find_tlb_idx()
225 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; in init_addr_map()
[all …]
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| A D | spl_minimal.c | 42 u32 s = mfspr(SPRN_TBRL); in udelay()
44 while ((mfspr(SPRN_TBRL) - s) < ticks); in udelay()
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| A D | start.S | 90 mfspr r3,SPRN_SVR
173 mfspr r1,DBSR
315 mfspr r3,PVR
369 mfspr r3, MAS1
385 mfspr r2, MAS2
398 mfspr r2, MAS3
888 mfspr r4, MAS2
1229 mfspr r4,DAR
1231 mfspr r5,DSISR
1320 mfspr r0,L1CSR1
[all …]
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| A D | traps.c | 147 mcsrr0 = mfspr(SPRN_MCSRR0); in MachineCheckException()
148 mcsrr1 = mfspr(SPRN_MCSRR1); in MachineCheckException()
149 mcsr = mfspr(SPRN_MCSR); in MachineCheckException()
150 mcar = mfspr(SPRN_MCAR); in MachineCheckException()
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| A D | cpu_init.c | 685 u32 l2cfg0 = mfspr(SPRN_L2CFG0); in l2cache_init()
689 while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC)) in l2cache_init()
701 while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E)) in l2cache_init()
778 mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS)); in cpu_init_r()
785 mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID)); in cpu_init_r()
794 if (mfspr(L1CSR2) & L1CSR2_DCWS) in cpu_init_r()
795 mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000)); in cpu_init_r()
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| A D | interrupts.c | 48 mtspr(SPRN_TCR, mfspr(SPRN_TCR) | TCR_PIE); in interrupt_init_cpu()
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| A D | fdt.c | 299 u32 l2cfg0 = mfspr(SPRN_L2CFG0); in ft_fixup_l2cache()
392 u32 l1cfg0 = mfspr(SPRN_L1CFG0); in ft_fixup_cache()
393 u32 l1cfg1 = mfspr(SPRN_L1CFG1); in ft_fixup_cache()
497 svr = mfspr(SPRN_SVR); in ft_fixup_qe_snum()
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| A D | cpu.c | 316 val = mfspr(DBCR0); in do_reset()
353 mtspr(SPRN_TCR, (mfspr(SPRN_TCR) & ~WATCHDOG_MASK) | in init_85xx_watchdog()
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| A D | mp.c | 29 return mfspr(SPRN_PIR); in get_my_id()
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| /u-boot/arch/powerpc/include/asm/ |
| A D | ppc.h | 44 return mfspr(SPRN_IMMR); in get_immr()
49 return mfspr(PVR); in get_pvr()
54 return mfspr(SVR); in get_svr()
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| A D | cache.h | 114 return mfspr(IC_CST); in rd_ic_cst()
129 return mfspr(DC_CST); in rd_dc_cst()
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| A D | processor.h | 1149 #define mfspr(rn) ({unsigned int rval; \ macro
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| /u-boot/arch/powerpc/cpu/mpc8xx/ |
| A D | cache.c | 16 return !!(mfspr(IC_CST) & IDC_ENABLED); in icache_status()
34 return !!(mfspr(IC_CST) & IDC_ENABLED); in dcache_status()
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| A D | start.S | 81 mfspr r3, ICR /* clear Interrupt Cause Register */
94 mfspr r3, IC_CST /* Clear error bits */
95 mfspr r3, DC_CST
202 mfspr r4,DAR
204 mfspr r5,DSISR
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| /u-boot/include/ |
| A D | ppc_asm.tmpl | 172 mfspr r20,SPRG0; \
174 mfspr r22,SPRG1; \
180 mfspr r20,XER; \
182 mfspr r20, DAR_DEAR; \
184 mfspr r22,reg1; \
185 mfspr r23,reg2; \
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| /u-boot/arch/powerpc/cpu/mpc83xx/ |
| A D | start.S | 324 mfspr r4,DAR
326 mfspr r5,DSISR
733 mfspr r3, HID0
746 mfspr r3, HID0
756 mfspr r3, HID0
763 mfspr r3, HID0
775 mfspr r3, HID0
788 mfspr r3, HID0
1073 mfspr r0, HID0
1097 mfspr r3, HID0
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| /u-boot/board/keymile/km83xx/ |
| A D | km83xx.c | 64 svid = SVR_REV(mfspr(SVR)); in board_early_init_r()
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| /u-boot/doc/ |
| A D | README.POST | 488 register will be checked as well (using mfspr). To verify the bc
|