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Searched refs:mhz (Results 1 – 25 of 31) sorted by relevance

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/u-boot/arch/arm/dts/
A Dmeson-g12b.dtsi51 capacity-dmips-mhz = <592>;
61 capacity-dmips-mhz = <592>;
71 capacity-dmips-mhz = <1024>;
81 capacity-dmips-mhz = <1024>;
91 capacity-dmips-mhz = <1024>;
101 capacity-dmips-mhz = <1024>;
A Dimx6sx-softing-vining-2000.dts436 pinctrl_usdhc2_50mhz: usdhc2grp-50mhz {
449 pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
460 pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
471 pinctrl_usdhc4_50mhz: usdhc4grp-50mhz {
487 pinctrl_usdhc4_100mhz: usdhc4-100mhz {
502 pinctrl_usdhc4_200mhz: usdhc4-200mhz {
A Dimx6sx-sabreauto.dts179 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
194 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
A Dvexpress-v2p-ca15_a7.dts44 capacity-dmips-mhz = <1024>;
54 capacity-dmips-mhz = <1024>;
64 capacity-dmips-mhz = <516>;
74 capacity-dmips-mhz = <516>;
84 capacity-dmips-mhz = <516>;
A Dhi3660.dtsi65 capacity-dmips-mhz = <592>;
79 capacity-dmips-mhz = <592>;
92 capacity-dmips-mhz = <592>;
105 capacity-dmips-mhz = <592>;
118 capacity-dmips-mhz = <1024>;
132 capacity-dmips-mhz = <1024>;
145 capacity-dmips-mhz = <1024>;
158 capacity-dmips-mhz = <1024>;
A Dstm32mp15-ddr3-1x4Gb-1066-binG.dtsi17 #define DDR_MEM_COMPATIBLE ddr3-1066-888-bin-g-1x4gb-533mhz
A Dstm32mp15-ddr3-2x4Gb-1066-binG.dtsi17 #define DDR_MEM_COMPATIBLE ddr3-1066-888-bin-g-2x4gb-533mhz
A Dstm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi18 #define DDR_MEM_COMPATIBLE ddr3l-dhsom-1066-888-bin-g-2x1gb-533mhz
A Dstm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi18 #define DDR_MEM_COMPATIBLE ddr3l-dhsom-1066-888-bin-g-2x2gb-533mhz
A Dstm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi18 #define DDR_MEM_COMPATIBLE ddr3l-dhsom-1066-888-bin-g-2x4gb-533mhz
A Dimx6-logicpd-baseboard.dtsi533 pinctrl_usdhc2_100mhz: h100-usdhc2-100mhz {
545 pinctrl_usdhc2_200mhz: h100-usdhc2-200mhz {
A Dimx6sx-sdb.dtsi627 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
642 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
A Dimx6ull-colibri.dtsi496 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
507 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
A Dr8a7790.dtsi82 capacity-dmips-mhz = <1024>;
103 capacity-dmips-mhz = <1024>;
124 capacity-dmips-mhz = <1024>;
145 capacity-dmips-mhz = <1024>;
166 capacity-dmips-mhz = <539>;
177 capacity-dmips-mhz = <539>;
188 capacity-dmips-mhz = <539>;
199 capacity-dmips-mhz = <539>;
A Dimx6qdl-hummingboard2.dtsi477 pinctrl_hummingboard2_usdhc2_100mhz: hummingboard2-usdhc2-100mhz {
488 pinctrl_hummingboard2_usdhc2_200mhz: hummingboard2-usdhc2-200mhz {
A Dam33xx-clocks.dtsi579 cpsw_125mhz_clkctrl: cpsw-125mhz-clkctrl@0 {
591 clk_24mhz_clkctrl: clk-24mhz-clkctrl@14c {
/u-boot/arch/xtensa/lib/
A Dtime.c54 ulong mhz = CONFIG_SYS_CLK_FREQ / 1000000; in __udelay() local
61 delay_cycles(mhz << 22); in __udelay()
62 delay_cycles(mhz * lo); in __udelay()
/u-boot/arch/xtensa/cpu/
A Dcpu.c32 char buf[120], mhz[8]; in print_cpuinfo() local
40 XCHAL_CORE_ID, id0, id1, strmhz(mhz, gd->cpu_clk)); in print_cpuinfo()
/u-boot/arch/arc/lib/
A Dcpu.c215 char mhz[8]; in print_cpuinfo() local
218 strmhz(mhz, gd->cpu_clk)); in print_cpuinfo()
/u-boot/drivers/ram/rockchip/
A Dsdram_rk3328.c80 u32 mhz = hz / MHZ; in rkclk_set_dpll() local
83 if (mhz <= 300) { in rkclk_set_dpll()
86 } else if (mhz <= 400) { in rkclk_set_dpll()
89 } else if (mhz <= 600) { in rkclk_set_dpll()
92 } else if (mhz <= 800) { in rkclk_set_dpll()
95 } else if (mhz <= 1600) { in rkclk_set_dpll()
102 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
A Dsdram_px30.c158 u32 mhz = hz / MHz; in rkclk_set_dpll() local
161 if (mhz <= 300) { in rkclk_set_dpll()
164 } else if (mhz <= 400) { in rkclk_set_dpll()
167 } else if (mhz <= 600) { in rkclk_set_dpll()
170 } else if (mhz <= 800) { in rkclk_set_dpll()
173 } else if (mhz <= 1600) { in rkclk_set_dpll()
180 fbdiv = (mhz * refdiv * postdiv1 * postdiv2) / 24; in rkclk_set_dpll()
/u-boot/board/hisilicon/hikey/
A DREADME125 INFO: succeed to set ddrc 150mhz
127 INFO: succeed to set ddrc 266mhz
129 INFO: succeed to set ddrc 400mhz
131 INFO: succeed to set ddrc 533mhz
133 INFO: succeed to set ddrc 800mhz
/u-boot/doc/device-tree-bindings/clock/
A Drockchip,rk3188-cru.txt34 - "xin27m" - 27mhz crystal input on rk3066 - optional,
/u-boot/arch/arm/mach-tegra/tegra124/
A Dclock.c1073 mhz = 1000 * 1000, min_vco = 500 * mhz, max_vco = 1000 * mhz, in clock_set_display_rate() local
1074 min_cf = 1 * mhz, max_cf = 6 * mhz; in clock_set_display_rate()
/u-boot/doc/device-tree-bindings/phy/
A Dphy-mtk-tphy.txt30 - mediatek,src-ref-clk-mhz : frequency of reference clock for slew rate

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