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Searched refs:miiphy_read (Results 1 – 25 of 32) sorted by relevance

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/u-boot/common/
A Dmiiphyutil.c361 if (miiphy_read(devname, addr, MII_BMCR, &reg) != 0) { in miiphy_reset()
417 if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) { in miiphy_speed()
427 if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) { in miiphy_speed()
434 if (miiphy_read(devname, addr, MII_LPA, &anlpar)) { in miiphy_speed()
467 if (miiphy_read(devname, addr, MII_LPA, &anlpar)) { in miiphy_duplex()
476 if (miiphy_read(devname, addr, MII_STAT1000, &btsr)) { in miiphy_duplex()
490 if (miiphy_read(devname, addr, MII_BMCR, &bmcr)) { in miiphy_duplex()
497 if (miiphy_read(devname, addr, MII_LPA, &anlpar)) { in miiphy_duplex()
527 if (miiphy_read(devname, addr, MII_ESTATUS, &exsr)) { in miiphy_is_1000base_x()
548 (void)miiphy_read(devname, addr, MII_BMSR, &reg); in miiphy_link()
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/u-boot/board/LaCie/common/
A Dcommon.c32 miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg); in mv_phy_88e1116_init()
52 miiphy_read(name, phyaddr, 16, &reg); in mv_phy_88e1318_init()
61 miiphy_read(name, phyaddr, MV88E1116_MAC_CTRL_REG, &reg); in mv_phy_88e1318_init()
/u-boot/board/zyxel/nsa310s/
A Dnsa310s.c95 if (miiphy_read(name, 0xee, 0xee, (u16 *) &phyaddr)) { in reset_phy()
102 miiphy_read(name, phyaddr, MV88E1318_MAC_CTRL_REG, &reg); in reset_phy()
119 miiphy_read(name, phyaddr, MV88E1318_LED_POL_REG, &reg); in reset_phy()
/u-boot/board/cloudengines/pogo_e02/
A Dpogo_e02.c87 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { in reset_phy()
97 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); in reset_phy()
/u-boot/board/Seagate/nas220/
A Dnas220.c101 if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { in reset_phy()
111 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); in reset_phy()
/u-boot/board/Marvell/dreamplug/
A Ddreamplug.c110 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { in mv_phy_88e1116_init()
121 miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, &reg); in mv_phy_88e1116_init()
/u-boot/board/Marvell/guruplug/
A Dguruplug.c113 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { in mv_phy_88e1121_init()
124 miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, &reg); in mv_phy_88e1121_init()
/u-boot/board/Marvell/sheevaplug/
A Dsheevaplug.c115 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { in reset_phy()
126 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); in reset_phy()
/u-boot/board/d-link/dns325/
A Ddns325.c115 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { in reset_phy()
125 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); in reset_phy()
/u-boot/board/Marvell/openrd/
A Dopenrd.c125 if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { in mv_phy_init()
135 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); in mv_phy_init()
/u-boot/board/Seagate/dockstar/
A Ddockstar.c120 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { in reset_phy()
131 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); in reset_phy()
/u-boot/board/Seagate/goflexhome/
A Dgoflexhome.c122 if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { in reset_phy()
133 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); in reset_phy()
/u-boot/board/gdsys/common/
A Dphy.c134 res = miiphy_read(bus, addr, reg, &orig_data); in process_setupcmd()
146 res = miiphy_read(bus, addr, reg, &orig_data); in process_setupcmd()
158 res = miiphy_read(bus, addr, reg, &orig_data); in process_setupcmd()
/u-boot/board/Synology/ds109/
A Dds109.c161 if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) { in reset_phy()
171 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg); in reset_phy()
/u-boot/board/freescale/ls1088a/
A Deth_ls1088aqds.c164 ret = miiphy_read(dev, phy_addr, 0x11, &value); in sgmii_configure_repeater()
205 ret = miiphy_read(dev, phy_addr, 0x11, &value); in sgmii_configure_repeater()
210 ret = miiphy_read(dev, phy_addr, 0x11, &value); in sgmii_configure_repeater()
297 ret = miiphy_read(dev, phy_addr, 0x11, &value); in qsgmii_configure_repeater()
299 ret = miiphy_read(dev, phy_addr, 0x11, &value); in qsgmii_configure_repeater()
336 ret = miiphy_read(dev, phy_addr, 0x11, &value); in qsgmii_configure_repeater()
340 ret = miiphy_read(dev, phy_addr, 0x11, &value); in qsgmii_configure_repeater()
/u-boot/drivers/net/
A Dbcm-sf2-eth.h52 int (*miiphy_read)(struct mii_dev *bus, int phyaddr, int devad, member
A Dmcfmii.c256 miiphy_read(dev->name, info->phy_addr, MII_BMCR, &status); in __mii_init()
267 miiphy_read(dev->name, info->phy_addr, MII_BMSR, &status); in __mii_init()
A Darmada100_fec.c375 if (miiphy_read(dev->name, addr, MII_BMSR, &mii_status) != 0) in ethernet_phy_detect()
384 if (miiphy_read(dev->name, addr, MII_PHYSID1, &tmp) != 0) in ethernet_phy_detect()
389 if (miiphy_read(dev->name, addr, MII_PHYSID2, &tmp) != 0) in ethernet_phy_detect()
510 miiphy_read(dev->name, 0xFF, 0xFF, &phy_adr); in armdfec_init()
/u-boot/board/freescale/ls2080aqds/
A Deth.c179 ret = miiphy_read(dev[mii_bus], riser_phy_addr[dpmac], 0x11, in sgmii_configure_repeater()
219 ret = miiphy_read(dev[mii_bus], in sgmii_configure_repeater()
226 ret = miiphy_read(dev[mii_bus], in sgmii_configure_repeater()
333 ret = miiphy_read(dev, phy_addr, 0x11, &value); in qsgmii_configure_repeater()
335 ret = miiphy_read(dev, phy_addr, 0x11, &value); in qsgmii_configure_repeater()
368 ret = miiphy_read(dev, phy_addr, 0x11, &value); in qsgmii_configure_repeater()
372 ret = miiphy_read(dev, phy_addr, 0x11, &value); in qsgmii_configure_repeater()
/u-boot/board/Marvell/gplugd/
A Dgplugd.c120 if (miiphy_read(name, 0xff, 0xff, &phy_adr)) { in reset_phy()
/u-boot/board/freescale/mx6qarm2/
A Dmx6qarm2.c185 miiphy_read("FEC", phy, MII_MMD_ACCESS_ADDR_DATA_REG, &val); in fecmxc_mii_postcall()
192 miiphy_read("FEC", phy, MII_DBG_PORT2_REG, &val); in fecmxc_mii_postcall()
/u-boot/cmd/
A Dmii.c372 if (miiphy_read (devname, addr, reg, &data) != 0) { in do_mii()
401 if (miiphy_read(devname, addr, in do_mii()
428 if (miiphy_read(devname, addr, reg, in do_mii()
/u-boot/board/egnite/ethernut5/
A Dethernut5.c171 if (miiphy_read(devname, 0, 18, &mode) == 0) { in board_eth_init()
/u-boot/drivers/net/phy/
A Dmv88e6352.c44 ret = miiphy_read(devname, phy_addr, COMMAND_REG, &command); in sw_wait_rdy()
80 ret = miiphy_read(devname, phy_addr, DATA_REG, data); in sw_reg_read()
/u-boot/include/
A Dmiiphy.h23 int miiphy_read(const char *devname, unsigned char addr, unsigned char reg,

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