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Searched refs:mmio_base (Results 1 – 18 of 18) sorted by relevance

/u-boot/arch/x86/cpu/intel_common/
A Dfast_spi.c50 ulong bar, mmio_base; in fast_spi_get_bios_mmap() local
54 mmio_base = bar & PCI_BASE_ADDRESS_MEM_MASK; in fast_spi_get_bios_mmap()
55 regs = (struct fast_spi_regs *)mmio_base; in fast_spi_get_bios_mmap()
60 int fast_spi_early_init(pci_dev_t pdev, ulong mmio_base) in fast_spi_early_init() argument
64 mmio_base | PCI_BASE_ADDRESS_SPACE_MEMORY, in fast_spi_early_init()
A Dp2sb.c66 pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0, plat->mmio_base, in p2sb_early_init()
98 plat->mmio_base = base[0]; in p2sb_of_to_plat()
106 upriv->mmio_base = plat->mmio_base; in p2sb_of_to_plat()
108 plat->mmio_base = plat->dtplat.early_regs[0]; in p2sb_of_to_plat()
110 upriv->mmio_base = plat->mmio_base; in p2sb_of_to_plat()
/u-boot/drivers/video/
A Dati_radeon_fb.h55 void *mmio_base; member
66 #define INREG8(addr) readb((rinfo->mmio_base)+addr)
67 #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
68 #define INREG16(addr) readw((rinfo->mmio_base)+addr)
69 #define OUTREG16(addr,val) writew(val, (rinfo->mmio_base)+addr)
70 #define INREG(addr) readl((rinfo->mmio_base)+addr)
71 #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
A Dati_radeon_fb.c574 rinfo->mmio_base = pci_bus_to_virt(pdev, rinfo->mmio_base_bus, in radeon_probe()
577 rinfo->mmio_base, rinfo->mmio_base_bus); in radeon_probe()
602 (u32)rinfo->mmio_base, rinfo->mmio_base_bus, in radeon_probe()
/u-boot/arch/x86/include/asm/
A Dp2sb.h14 ulong mmio_base; member
A Dfast_spi.h88 int fast_spi_early_init(pci_dev_t pdev, ulong mmio_base);
/u-boot/drivers/misc/
A Dp2sb_sandbox.c23 upriv->mmio_base = dm_pci_read_bar32(dev, 0); in sandbox_p2sb_probe()
A Dp2sb-uclass.c39 reg_addr = upriv->mmio_base; in pcr_reg_address()
/u-boot/drivers/pci/
A Dpci_ftpci100.c24 unsigned int mmio_base; member
94 addr_mem_base = &priv->mmio_base; in setup_pci_bar()
232 priv->mmio_base = CONFIG_FTPCI100_MEM_BASE; in ftpci_preinit()
/u-boot/drivers/spi/
A Dich.c685 ulong mmio_base; in ich_get_mmap_bus() local
689 &ich_version, &mmio_base); in ich_get_mmap_bus()
692 regs = (struct fast_spi_regs *)mmio_base; in ich_get_mmap_bus()
787 ret = fast_spi_early_init(plat->bdf, plat->mmio_base); in ich_init_controller()
792 ctlr->base = (void *)plat->mmio_base; in ich_init_controller()
834 plat->ich_version, plat->mmio_base, ctlr->max_speed); in ich_init_controller()
946 &plat->mmio_base); in ich_spi_of_to_plat()
957 plat->mmio_base = plat->dtplat.early_regs[0]; in ich_spi_of_to_plat()
961 debug("%s: mmio_base=%lx\n", __func__, plat->mmio_base); in ich_spi_of_to_plat()
A Dich.h239 ulong mmio_base; /* Base of MMIO registers */ member
/u-boot/drivers/ata/
A Dahci.c182 void __iomem *mmio = uc_priv->mmio_base; in ahci_host_init()
194 ret = ahci_reset(uc_priv->mmio_base); in ahci_host_init()
359 void __iomem *mmio = uc_priv->mmio_base; in ahci_print_info()
454 uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5, in ahci_init_one()
465 uc_priv->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5, in ahci_init_one()
478 uc_priv->mmio_base = (void *)plat->base; in ahci_init_one()
481 debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base); in ahci_init_one()
1060 uc_priv->mmio_base = base; in ahci_init_common()
A Ddwc_ahsata.c111 struct sata_host_regs *host_mmio = uc_priv->mmio_base; in ahci_setup_oobr()
124 struct sata_host_regs *host_mmio = uc_priv->mmio_base; in ahci_host_init()
278 struct sata_host_regs *host_mmio = uc_priv->mmio_base; in ahci_print_info()
866 uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR; in ahci_init_one()
921 host_mmio = uc_priv->mmio_base; in reset_sata()
991 struct sata_host_regs *host_mmio = uc_priv->mmio_base; in dwc_ahsata_bus_reset()
1042 uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev); in dwc_ahsata_probe()
/u-boot/include/
A Dp2sb.h36 uint mmio_base; member
A Dahci.h167 void __iomem *mmio_base; member
/u-boot/drivers/ufs/
A Dufs.h706 void __iomem *mmio_base; member
905 writel((val), (hba)->mmio_base + (reg))
907 readl((hba)->mmio_base + (reg))
A Dufs.c1883 hba->mmio_base = (void *)dev_read_addr(ufs_dev); in ufshcd_probe()
/u-boot/drivers/mtd/nand/raw/
A Dpxa3xx_nand.c138 writel((val), (info)->mmio_base + (off))
141 readl((info)->mmio_base + (off))
190 void __iomem *mmio_base; member
622 readsl(info->mmio_base + NDDB, data, 8); in drain_fifo()
638 readsl(info->mmio_base + NDDB, data, len); in drain_fifo()
656 writesl(info->mmio_base + NDDB, in handle_data_pio()
661 writesl(info->mmio_base + NDDB, in handle_data_pio()
1857 info->mmio_base = dev_read_addr_ptr(dev); in pxa3xx_nand_probe_dt()

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