| /u-boot/drivers/video/nexell/ |
| A D | s5pxx18_dp.c | 26 void dp_control_init(int module) in dp_control_init() argument 36 nx_dpc_set_base_address(module, base); in dp_control_init() 49 int dp_control_setup(int module, in dp_control_setup() argument 70 module); in dp_control_setup() 174 __func__, module, in dp_control_setup() 190 nx_dpc_set_dpc_enable(module, on); in dp_control_enable() 194 void dp_plane_init(int module) in dp_plane_init() argument 220 nx_mlc_set_gamma_priority(module, 0); in dp_plane_screen_setup() 235 nx_mlc_set_mlc_enable(module, on); in dp_plane_screen_enable() 236 nx_mlc_set_top_dirty_flag(module); in dp_plane_screen_enable() [all …]
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| A D | s5pxx18_dp_rgb.c | 22 switch (module) { in rgb_switch() 38 void nx_rgb_display(int module, in nx_rgb_display() argument 48 printf("RGB: dp.%d\n", module); in nx_rgb_display() 50 dp_control_init(module); in nx_rgb_display() 51 dp_plane_init(module); in nx_rgb_display() 54 dp_plane_screen_setup(module, top); in nx_rgb_display() 59 dp_plane_layer_setup(module, plane); in nx_rgb_display() 63 dp_plane_screen_enable(module, 1); in nx_rgb_display() 65 rgb_switch(module, input, sync, dev); in nx_rgb_display() 67 dp_control_setup(module, sync, ctrl); in nx_rgb_display() [all …]
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| A D | s5pxx18_dp_lvds.c | 54 static int lvds_setup(int module, int input, in lvds_setup() argument 237 void nx_lvds_display(int module, in nx_lvds_display() argument 247 printf("LVDS: dp.%d\n", module); in nx_lvds_display() 249 dp_control_init(module); in nx_lvds_display() 250 dp_plane_init(module); in nx_lvds_display() 255 dp_plane_screen_setup(module, top); in nx_lvds_display() 260 dp_plane_layer_setup(module, plane); in nx_lvds_display() 261 dp_plane_layer_enable(module, plane, 1); in nx_lvds_display() 264 dp_plane_screen_enable(module, 1); in nx_lvds_display() 272 dp_control_setup(module, sync, ctrl); in nx_lvds_display() [all …]
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| A D | s5pxx18_dp_mipi.c | 359 nx_disp_top_set_mipimux(1, module); in mipi_enable() 625 void nx_mipi_display(int module, in nx_mipi_display() argument 636 printf("MIPI: dp.%d\n", module); in nx_mipi_display() 647 dp_control_init(module); in nx_mipi_display() 648 dp_plane_init(module); in nx_mipi_display() 653 dp_plane_screen_setup(module, top); in nx_mipi_display() 658 dp_plane_layer_setup(module, plane); in nx_mipi_display() 659 dp_plane_layer_enable(module, plane, 1); in nx_mipi_display() 661 dp_plane_screen_enable(module, 1); in nx_mipi_display() 675 dp_control_setup(module, sync, ctrl); in nx_mipi_display() [all …]
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| A D | s5pxx18_dp_hdmi.c | 492 void nx_hdmi_display(int module, in nx_hdmi_display() argument 498 int input = module == 0 ? DP_DEVICE_DP0 : DP_DEVICE_DP1; in nx_hdmi_display() 503 debug("HDMI: display.%d\n", module); in nx_hdmi_display() 526 dp_control_init(module); in nx_hdmi_display() 527 dp_plane_init(module); in nx_hdmi_display() 532 dp_plane_screen_setup(module, top); in nx_hdmi_display() 536 dp_plane_layer_setup(module, plane); in nx_hdmi_display() 537 dp_plane_layer_enable(module, plane, 1); in nx_hdmi_display() 539 dp_plane_screen_enable(module, 1); in nx_hdmi_display() 541 dp_control_setup(module, sync, ctrl); in nx_hdmi_display() [all …]
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| /u-boot/arch/arm/mach-nexell/include/mach/ |
| A D | display.h | 216 int module; member 226 void nx_lvds_display(int module, 232 void nx_rgb_display(int module, 237 void nx_hdmi_display(int module, 243 void nx_mipi_display(int module, 252 void dp_control_init(int module); 255 void dp_control_enable(int module, int on); 257 void dp_plane_init(int module); 259 void dp_plane_screen_enable(int module, int on); 264 int dp_plane_set_enable(int module, int layer, int on); [all …]
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| /u-boot/arch/arm/dts/ |
| A D | omap4-u-boot.dtsi | 11 target-module@2000 { 16 target-module@64000 { 25 target-module@20000 { 30 target-module@70000 { 35 target-module@9c000 {
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| A D | omap5-u-boot.dtsi | 114 target-module@2000 { 119 target-module@64000 { 128 target-module@20000 { 133 target-module@70000 { 138 target-module@9c000 { 143 target-module@b4000 {
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| A D | am33xx-l4.dtsi | 33 target-module@0 { /* 0x44d00000, ap 4 28.0 */ 43 target-module@80000 { /* 0x44d80000, ap 6 10.0 */ 89 target-module@0 { /* 0x44e00000, ap 8 58.0 */ 114 target-module@3000 { /* 0x44e03000, ap 10 0a.0 */ 122 target-module@5000 { /* 0x44e05000, ap 12 30.0 */ 175 target-module@9000 { /* 0x44e09000, ap 16 04.0 */ 206 target-module@b000 { /* 0x44e0b000, ap 18 48.0 */ 229 target-module@d000 { /* 0x44e0d000, ap 20 38.0 */ 492 target-module@c000 { /* 0x47c0c000, ap 3 04.0 */ 746 target-module@0 { /* 0x4b140000, ap 5 02.2 */ [all …]
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| A D | omap5-l4.dtsi | 52 target-module@2000 { /* 0x4a002000, ap 3 44.0 */ 117 target-module@4000 { /* 0x4a004000, ap 5 5c.0 */ 143 target-module@8000 { /* 0x4a008000, ap 21 4c.0 */ 168 target-module@20000 { /* 0x4a020000, ap 109 08.0 */ 214 target-module@56000 { /* 0x4a056000, ap 7 02.0 */ 251 target-module@58000 { /* 0x4a058000, ap 10 06.0 */ 262 target-module@5e000 { /* 0x4a05e000, ap 69 2a.0 */ 270 target-module@62000 { /* 0x4a062000, ap 11 0e.0 */ 435 target-module@0 { /* 0x4a080000, ap 83 28.0 */ 2278 target-module@0 { /* 0x4ae10000, ap 5 10.0 */ [all …]
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| A D | omap4-l4.dtsi | 44 target-module@2000 { /* 0x4a002000, ap 3 06.0 */ 87 target-module@4000 { /* 0x4a004000, ap 5 02.0 */ 112 target-module@8000 { /* 0x4a008000, ap 23 32.0 */ 137 target-module@56000 { /* 0x4a056000, ap 7 0a.0 */ 174 target-module@58000 { /* 0x4a058000, ap 10 0e.0 */ 233 target-module@5e000 { /* 0x4a05e000, ap 80 68.0 */ 241 target-module@62000 { /* 0x4a062000, ap 11 16.0 */ 420 ctrl-module = <&omap_control_usbotg>; 452 ctrl-module = <&omap_control_usb2phy>; 655 target-module@0 { /* 0x4a100000, ap 21 2a.0 */ [all …]
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| A D | omap4-mcpdm.dtsi | 6 * pmic to ABE as mcpdm uses an external clock for the module. 32 * McPDM pads must be muxed at the interconnect target module 33 * level as the module on the SoC needs external clock from
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| A D | omap5-l4-abe.dtsi | 87 target-module@22000 { /* 0x40122000, ap 2 02.0 */ 120 target-module@24000 { /* 0x40124000, ap 4 04.0 */ 153 target-module@26000 { /* 0x40126000, ap 6 06.0 */ 186 target-module@28000 { /* 0x40128000, ap 8 08.0 */ 195 target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */ 204 target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */ 235 target-module@30000 { /* 0x40130000, ap 14 0e.0 */ 278 target-module@38000 { /* 0x40138000, ap 18 12.0 */ 309 target-module@3a000 { /* 0x4013a000, ap 20 14.0 */ 340 target-module@3c000 { /* 0x4013c000, ap 22 16.0 */ [all …]
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| A D | omap4-l4-abe.dtsi | 87 target-module@22000 { /* 0x40122000, ap 2 02.0 */ 120 target-module@24000 { /* 0x40124000, ap 4 04.0 */ 153 target-module@26000 { /* 0x40126000, ap 6 06.0 */ 186 target-module@28000 { /* 0x40128000, ap 8 08.0 */ 211 target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */ 220 target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */ 251 target-module@30000 { /* 0x40130000, ap 14 0e.0 */ 313 target-module@38000 { /* 0x40138000, ap 18 12.0 */ 343 target-module@3a000 { /* 0x4013a000, ap 20 14.0 */ 373 target-module@3c000 { /* 0x4013c000, ap 22 16.0 */ [all …]
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| /u-boot/arch/arm/mach-rockchip/rk3368/ |
| A D | Kconfig | 7 bool "Theobroma Systems RK3368-uQ7 (Lion) module" 10 MXM-230 connector) system-on-module designed by Theobroma 15 - (on-module) up to 4GB of DDR3 memory 16 - (on-module) SPI-NOR flash 17 - (on-module) eMMC 18 - Gigabit Ethernet (with an on-module KSZ9031 PHY) 23 - on-module STM32 providing CAN, RTC and fan-control 24 - (optional on-module) EAL4+-certified security module
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| /u-boot/tools/buildman/ |
| A D | buildman | 37 for module in ['buildman.toolchain', 'patman.gitutil']: 38 suite = doctest.DocTestSuite(module) 44 for module in (test.TestBuild, func_test.TestFunctional): 45 suite = unittest.TestLoader().loadTestsFromTestCase(module)
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| A D | main.py | 37 for module in ['buildman.toolchain', 'patman.gitutil']: 38 suite = doctest.DocTestSuite(module) 44 for module in (test.TestBuild, func_test.TestFunctional): 45 suite = unittest.TestLoader().loadTestsFromTestCase(module)
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| /u-boot/board/toradex/colibri_imx7/ |
| A D | Kconfig | 11 256MB or Colibri iMX7D 512MB module which do have raw NAND 12 on-module. 18 1GB module which does have eMMC on-module. 34 Select this if your module provides a external Ethernet PHY
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| /u-boot/scripts/kconfig/ |
| A D | streamline_config.pl | 398 foreach my $module (keys(%modules)) { 399 if (defined($objects{$module})) { 400 my @arr = @{$objects{$module}}; 402 $configs{$conf} = $module; 403 dprint "$conf added by direct ($module)\n"; 416 print STDERR "$module config not found!!\n"; 668 foreach my $module (keys(%modules)) { 669 if (defined($objects{$module})) { 670 my @arr = @{$objects{$module}}; 676 print STDERR "module $module did not have configs";
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| /u-boot/tools/patman/ |
| A D | test_util.py | 159 for module in []: 160 suite = doctest.DocTestSuite(module) 174 for module in test_class_list: 176 if hasattr(module, 'setup_test_args'): 177 setup_test_args = getattr(module, 'setup_test_args') 183 suite.addTests(loader.loadTestsFromName(test_name, module)) 187 suite.addTests(loader.loadTestsFromTestCase(module))
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| /u-boot/board/freescale/s32v234evb/ |
| A D | lpddr2.c | 14 void lpddr2_config_iomux(uint8_t module) in lpddr2_config_iomux() argument 18 switch (module) { in lpddr2_config_iomux() 65 void config_mmdc(uint8_t module) in config_mmdc() argument 67 unsigned long mmdc_addr = (module) ? MMDC1_BASE_ADDR : MMDC0_BASE_ADDR; in config_mmdc() 105 switch (module) { in config_mmdc()
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| /u-boot/arch/mips/dts/ |
| A D | jz4780.dtsi | 78 clock-names = "baud", "module"; 92 clock-names = "baud", "module"; 106 clock-names = "baud", "module"; 120 clock-names = "baud", "module"; 134 clock-names = "baud", "module";
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| /u-boot/arch/arm/include/asm/mach-imx/ |
| A D | module_fuse.h | 70 enum fuse_module_type module; member 78 static inline u32 check_module_fused(enum fuse_module_type module) in check_module_fused() argument 118 u32 check_module_fused(enum fuse_module_type module);
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| /u-boot/doc/device-tree-bindings/fsp/fsp2/apollolake/ |
| A D | fsp-m.txt | 287 /* DQA[0:7] pins of LPDDR4 module */ 289 /* DQA[8:15] pins of LPDDR4 module */ 291 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ 297 /* DQA[0:7] pins of LPDDR4 module */ 299 /* DQA[8:15] pins of LPDDR4 module */ 301 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ 308 /* DQA[0:7] pins of LPDDR4 module */ 310 /* DQA[8:15] pins of LPDDR4 module */ 312 /* DQB[0:7] pins of LPDDR4 module with offset of 16 */ 319 /* DQA[0:7] pins of LPDDR4 module */ [all …]
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| /u-boot/drivers/bus/ |
| A D | Kconfig | 15 bool "TI sysc interconnect target module driver" 18 Generic driver for Texas Instruments interconnect target module
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