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Searched refs:mpll_mdiv (Results 1 – 2 of 2) sorted by relevance

/u-boot/arch/arm/mach-exynos/
A Dclock_init.h47 unsigned mpll_mdiv; member
A Dclock_init_exynos5.c144 .mpll_mdiv = 0xc8,
268 .mpll_mdiv = 0xc8,
371 .mpll_mdiv = 0xc8,
627 val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); in exynos5250_system_clock_init()
848 val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); in exynos5420_system_clock_init()

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