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Searched refs:mr (Results 1 – 25 of 96) sorted by relevance

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/u-boot/post/lib_powerpc/
A Dasm.S26 mr r3, r4
27 mr r4, r5
49 mr r3, r4
50 mr r4, r5
51 mr r5, r6
72 mr r3, r5
73 mr r4, r6
93 mr r3, r5
119 mr r3, r6
149 mr r3, r6
[all …]
/u-boot/arch/arm/mach-at91/
A Dsdram.c37 writel(AT91_SDRAMC_MODE_NOP, &reg->mr); in sdramc_initialize()
41 writel(AT91_SDRAMC_MODE_PRECHARGE, &reg->mr); in sdramc_initialize()
49 writel(AT91_SDRAMC_MODE_REFRESH, &reg->mr); in sdramc_initialize()
57 writel(AT91_SDRAMC_MODE_LMR, &reg->mr); in sdramc_initialize()
65 writel(AT91_SDRAMC_MODE_NORMAL, &reg->mr); in sdramc_initialize()
A Dphy.c29 erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; in at91_phy_reset()
38 AT91_RSTC_MR_URSTEN, &rstc->mr); in at91_phy_reset()
56 writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); in at91_phy_reset()
/u-boot/arch/arm/mach-imx/imx8/
A Dcpu.c247 owned = sc_rm_is_memreg_owned(-1, mr); in get_owned_memreg()
277 sc_rm_mr_t mr; in get_effective_memsize() local
288 for (mr = 0; mr < 64; mr++) { in get_effective_memsize()
289 err = get_owned_memreg(mr, &start, &end); in get_effective_memsize()
315 sc_rm_mr_t mr; in dram_init() local
326 for (mr = 0; mr < 64; mr++) { in dram_init()
327 err = get_owned_memreg(mr, &start, &end); in dram_init()
382 sc_rm_mr_t mr; in dram_init_banksize() local
394 for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) { in dram_init_banksize()
489 sc_rm_mr_t mr; in enable_caches() local
[all …]
A Dparse-container.c23 sc_rm_mr_t mr; in authenticate_image() local
31 err = sc_rm_find_memreg(-1, &mr, in authenticate_image()
41 err = sc_rm_get_memreg_info(-1, mr, &start, &end); in authenticate_image()
43 debug("memreg %u 0x%x -- 0x%x\n", mr, start, end); in authenticate_image()
45 err = sc_rm_set_memreg_permissions(-1, mr, in authenticate_image()
61 err = sc_rm_set_memreg_permissions(-1, mr, in authenticate_image()
A Dahab.c49 sc_rm_mr_t mr; in authenticate_os_container() local
109 err = sc_rm_find_memreg(-1, &mr, s, e); in authenticate_os_container()
116 err = sc_rm_get_memreg_info(-1, mr, &start, &end); in authenticate_os_container()
118 debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end); in authenticate_os_container()
120 err = sc_rm_set_memreg_permissions(-1, mr, SECO_PT, in authenticate_os_container()
137 err = sc_rm_set_memreg_permissions(-1, mr, SECO_PT, in authenticate_os_container()
/u-boot/arch/arm/mach-omap2/
A Demif-common.c62 u32 mr; in get_mr() local
73 if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) && in get_mr()
74 ((mr & 0x00ff0000) >> 16) == (mr & 0xff) && in get_mr()
75 ((mr & 0xff000000) >> 24) == (mr & 0xff)) in get_mr()
76 return mr & 0xff; in get_mr()
78 return mr; in get_mr()
1119 u32 mr = 0, temp; in is_lpddr2_sdram_present() local
1122 if (mr > 0xFF) { in is_lpddr2_sdram_present()
1140 if (mr > 0xFF) { in is_lpddr2_sdram_present()
1146 if (mr > 0xFF) { in is_lpddr2_sdram_present()
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/u-boot/arch/arm/mach-sunxi/
A Ddram_sun9i.c364 u16 mr[4] = { 0, }; in mctl_channel_init() local
464 mr[1] = DDR3_MR1_RTT120OHM; in mctl_channel_init()
465 mr[2] = DDR3_MR2_TWL(CWL); in mctl_channel_init()
466 mr[3] = 0; in mctl_channel_init()
485 writel(MCTL_INIT3_MR(mr[0]) | MCTL_INIT3_EMR(mr[1]), in mctl_channel_init()
487 writel(MCTL_INIT4_EMR2(mr[2]) | MCTL_INIT4_EMR3(mr[3]), in mctl_channel_init()
506 writel(MCTL_INIT3_MR(mr[1]) | MCTL_INIT3_EMR(mr[2]), in mctl_channel_init()
634 writel(mr[0], &mctl_phy->mr0); in mctl_channel_init()
635 writel(mr[1], &mctl_phy->mr1); in mctl_channel_init()
636 writel(mr[2], &mctl_phy->mr2); in mctl_channel_init()
[all …]
/u-boot/arch/arm/mach-sunxi/dram_timings/
A Dddr2_v3s.c48 writel(0x263, &mctl_ctl->mr[0]); in mctl_set_timing_params()
49 writel(0x4, &mctl_ctl->mr[1]); in mctl_set_timing_params()
50 writel(0x0, &mctl_ctl->mr[2]); in mctl_set_timing_params()
51 writel(0x0, &mctl_ctl->mr[3]); in mctl_set_timing_params()
A Dddr3_1333.c48 writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */ in mctl_set_timing_params()
49 writel(0x40, &mctl_ctl->mr[1]); in mctl_set_timing_params()
50 writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */ in mctl_set_timing_params()
51 writel(0x0, &mctl_ctl->mr[3]); in mctl_set_timing_params()
A Dlpddr3_stock.c48 writel(0xc3, &mctl_ctl->mr[1]); /* nWR=8, BL8 */ in mctl_set_timing_params()
49 writel(0xa, &mctl_ctl->mr[2]); /* RL=12, WL=6 */ in mctl_set_timing_params()
50 writel(0x2, &mctl_ctl->mr[3]); /* 40 0hms PD/PU */ in mctl_set_timing_params()
/u-boot/drivers/dma/
A Dfsl_dma.c73 out_dma32(&dma->mr, in_dma32(&dma->mr) & ~FSL_DMA_MR_CS); in dma_check()
112 out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT); in dmacpy()
116 out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT | FSL_DMA_MR_CS); in dmacpy()
/u-boot/arch/arm/mach-omap2/omap3/
A Dsdrc.c42 if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) in is_mem_sdr()
115 writel(timings->mr, &sdrc_base->cs[cs].mr); in write_sdrc_timings()
190 timings.mr = readl(&sdrc_base->cs[CS0].mr); in do_sdrc_init()
/u-boot/arch/arm/mach-omap2/am33xx/
A Dddr.c43 u32 mr; in get_mr() local
48 mr = readl(&emif_reg[nr]->emif_lpddr2_mode_reg_data); in get_mr()
49 debug("get_mr: EMIF1 cs %d mr %08x val 0x%x\n", cs, mr_addr, mr); in get_mr()
50 if (((mr & 0x0000ff00) >> 8) == (mr & 0xff) && in get_mr()
51 ((mr & 0x00ff0000) >> 16) == (mr & 0xff) && in get_mr()
52 ((mr & 0xff000000) >> 24) == (mr & 0xff)) in get_mr()
53 return mr & 0xff; in get_mr()
55 return mr; in get_mr()
/u-boot/drivers/rtc/
A Dat91sam9_rtt.c57 writel(32768+AT91_RTT_RTTRST, &rtt->mr); in rtc_set()
72 writel(32768+AT91_RTT_RTTRST, &rtt->mr); in rtc_reset()
/u-boot/examples/api/
A Dglue.c118 static struct mem_region mr[UB_MAX_MR]; variable
126 si.mr = mr; in ub_get_sys_info()
128 memset(&mr, 0, sizeof(mr)); in ub_get_sys_info()
A Ddemo.c220 if (si->mr[i].flags == 0) in test_dump_si()
223 printf(" start\t= 0x%08lx\n", si->mr[i].start); in test_dump_si()
224 printf(" size\t= 0x%08lx\n", si->mr[i].size); in test_dump_si()
226 switch(si->mr[i].flags & 0x000F) { in test_dump_si()
/u-boot/arch/arm/mach-at91/include/mach/
A Dat91_mc.h31 u32 mr; /* 0x00 SDRAMC Mode Register */ member
63 u32 mr; /* 0x00 SDRAMC Mode Register */ member
A Dat91_rtt.h16 u32 mr; /* Mode Register RW 0x00008000 */ member
A Dat91_pit.h16 u32 mr; /* 0x00 Mode Register */ member
/u-boot/arch/sandbox/cpu/
A Deth-raw-os.c71 struct packet_mreq mr; in _raw_packet_start() local
109 mr.mr_ifindex = device->sll_ifindex; in _raw_packet_start()
110 mr.mr_type = PACKET_MR_PROMISC; in _raw_packet_start()
112 &mr, sizeof(mr)); in _raw_packet_start()
/u-boot/arch/m68k/cpu/mcf532x/
A Dcpu.c136 out_be16(&wdp->mr, wdog_module / 8192); in watchdog_init()
138 out_be16(&wdp->mr, wdog_module / 4096); in watchdog_init()
/u-boot/arch/powerpc/include/asm/
A Dfsl_dma.h15 uint mr; /* DMA mode register */ member
49 uint mr; /* DMA mode register */ member
/u-boot/arch/arm/include/asm/arch-imx8/sci/
A Dsci.h92 sc_bool_t sc_rm_is_memreg_owned(sc_ipc_t ipc, sc_rm_mr_t mr);
93 int sc_rm_find_memreg(sc_ipc_t ipc, sc_rm_mr_t *mr, sc_faddr_t addr_start,
95 int sc_rm_set_memreg_permissions(sc_ipc_t ipc, sc_rm_mr_t mr,
97 int sc_rm_get_memreg_info(sc_ipc_t ipc, sc_rm_mr_t mr, sc_faddr_t *addr_start,
/u-boot/arch/powerpc/cpu/mpc8xx/
A Dstart.S337 mr r1, r3 /* Set new stack pointer */
338 mr r9, r4 /* Save copy of Global Data pointer */
339 mr r10, r5 /* Save copy of Destination Address */
342 mr r3, r5 /* Destination Address */
398 mr r4,r3
404 mr r4,r3
479 mr r3, r9 /* Global Data pointer */
480 mr r4, r10 /* Destination Address */

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