| /u-boot/board/ti/ks2_evm/ |
| A D | ddr3_k2g.c | 30 .mr0 = 0x00001430ul,
70 .mr0 = 0x00001830ul,
131 .mr0 = 0x00001430ul,
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| A D | ddr3_cfg.c | 28 .mr0 = 0x00001C70ul,
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| /u-boot/arch/nds32/cpu/n1213/ |
| A D | start.S | 124 mfsr $r1, $mr0
126 mtsr $r1, $mr0
137 mfsr $r1, $mr0
139 mtsr $r1, $mr0
148 mfsr $r1, $mr0
150 mtsr $r1, $mr0
155 mfsr $r1, $mr0
157 mtsr $r1, $mr0
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| /u-boot/arch/arm/mach-sunxi/ |
| A D | dram_sun8i_a23.c | 39 .mr0 = 6736,
116 writel(dram_para.mr0, &mctl_phy->mr0); in mctl_init()
202 writel((dram_para.mr0 << 16) | dram_para.mr1, &mctl_ctl->init3); in mctl_init()
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| A D | dram_sun8i_a83t.c | 136 writel(MCTL_MR0, &mctl_ctl->mr0); in auto_set_timing_para()
141 writel(MCTL_LPDDR3_MR0, &mctl_ctl->mr0); in auto_set_timing_para()
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| A D | dram_sun8i_a33.c | 135 writel(MCTL_MR0, &mctl_ctl->mr0); in auto_set_timing_para()
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| A D | dram_sun6i.c | 124 writel(MCTL_MR0, &mctl_phy->mr0); in mctl_channel_init()
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| A D | dram_sun9i.c | 634 writel(mr[0], &mctl_phy->mr0); in mctl_channel_init()
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| /u-boot/arch/arm/mach-keystone/include/mach/ |
| A D | ddr3.h | 28 unsigned int mr0; member
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| /u-boot/board/imgtec/ci20/ |
| A D | ci20.c | 290 .mr0 = 0x420,
334 .mr0 = 0x420,
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| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| A D | dram_sun8i_a23.h | 24 u32 mr0; member
184 u32 mr0; /* 0x54 mode register 0 */ member
|
| A D | dram_sun8i_a33.h | 78 u32 mr0; /* 0x30 */ member
|
| A D | dram_sun8i_a83t.h | 78 u32 mr0; /* 0x30 */ member
|
| A D | dram_sun9i.h | 111 u32 mr0; /* 0x9c mode register 0 */ member
|
| A D | dram_sun6i.h | 177 u32 mr0; /* 0x40 mode register 0 */ member
|
| /u-boot/drivers/ram/stm32mp1/ |
| A D | stm32mp1_ddr.h | 137 u32 mr0; member
|
| A D | stm32mp1_ddr_regs.h | 158 u32 mr0; /* 0x40 Mode 0*/ member
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| A D | stm32mp1_ddr.c | 175 DDRPHY_REG_TIMING(mr0),
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| /u-boot/arch/arm/mach-keystone/ |
| A D | ddr3_spd.c | 35 debug_ddr_cfg("mr0 0x%08X\n", ptr->mr0); in dump_phy_config()
347 spd_cb->phy_cfg.mr0 = 1 << 12 | (spd->t_wr_bin & 0x7) << 9 | 0 << 8 | in init_ddr3param()
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| A D | ddr3.c | 55 __raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET); in ddr3_init_ddrphy()
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| /u-boot/arch/mips/mach-jz47xx/jz4780/ |
| A D | sdram.c | 78 writel(ddr_config->mr0, ddr_phy_regs + DDRP_MR0); in ddr_phy_init()
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| /u-boot/arch/mips/mach-jz47xx/include/mach/ |
| A D | jz4780_dram.h | 438 u16 mr0; /* Mode Register 0 */ member
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| /u-boot/doc/device-tree-bindings/clock/ |
| A D | rockchip,rk3288-dmc.txt | 92 mr0..mr3
|