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Searched refs:mr2 (Results 1 – 22 of 22) sorted by relevance

/u-boot/board/ti/ks2_evm/
A Dddr3_k2g.c32 .mr2 = 0x00000000ul,
72 .mr2 = 0x00000000ul,
133 .mr2 = 0x00000008ul,
A Dddr3_cfg.c30 .mr2 = 0x00000018ul,
/u-boot/arch/arm/mach-sunxi/
A Ddram_sun8i_a23.c41 .mr2 = 16,
118 writel(dram_para.mr2, &mctl_phy->mr2); in mctl_init()
203 writel((dram_para.mr2 << 16) | dram_para.mr3, &mctl_ctl->init4); in mctl_init()
A Ddram_sun8i_a83t.c138 writel(MCTL_MR2, &mctl_ctl->mr2); in auto_set_timing_para()
143 writel(MCTL_LPDDR3_MR2, &mctl_ctl->mr2); in auto_set_timing_para()
A Ddram_sun8i_a33.c137 writel(MCTL_MR2, &mctl_ctl->mr2); in auto_set_timing_para()
A Ddram_sun6i.c126 writel(MCTL_MR2, &mctl_phy->mr2); in mctl_channel_init()
A Ddram_sun9i.c636 writel(mr[2], &mctl_phy->mr2); in mctl_channel_init()
/u-boot/arch/arm/mach-keystone/include/mach/
A Dddr3.h30 unsigned int mr2; member
/u-boot/arch/arm/include/asm/arch-sunxi/
A Ddram_sun8i_a23.h26 u32 mr2; member
186 u32 mr2; /* 0x5c mode register 2 */ member
A Ddram_sun8i_a33.h80 u32 mr2; /* 0x38 */ member
A Ddram_sun8i_a83t.h80 u32 mr2; /* 0x38 */ member
A Ddram_sun9i.h113 u32 mr2; /* 0xa4 mode register 2 */ member
A Ddram_sun6i.h179 u32 mr2; /* 0x48 mode register 2 */ member
/u-boot/drivers/ram/stm32mp1/
A Dstm32mp1_ddr.h139 u32 mr2; member
A Dstm32mp1_ddr_regs.h160 u32 mr2; /* 0x48 Mode 2*/ member
A Dstm32mp1_ddr.c177 DDRPHY_REG_TIMING(mr2),
/u-boot/arch/arm/mach-omap2/omap4/
A Dsdram_elpida.c310 .mr2 = 0x4,
/u-boot/arch/arm/mach-keystone/
A Dddr3_spd.c37 debug_ddr_cfg("mr2 0x%08X\n", ptr->mr2); in dump_phy_config()
356 spd_cb->phy_cfg.mr2 = DYN_ODT << 9 | TEMP << 7 | (spd->asr & 1) << 6 | in init_ddr3param()
A Dddr3.c57 __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET); in ddr3_init_ddrphy()
/u-boot/arch/arm/mach-omap2/omap5/
A Dsdram.c442 .mr2 = 0x6,
/u-boot/arch/arm/include/asm/
A Demif.h1244 s8 mr2; member
/u-boot/arch/arm/mach-omap2/
A Demif-common.c125 set_mr(base, cs, mr_addr, mr_regs->mr2); in do_lpddr2_init()

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