Searched refs:mr3 (Results 1 – 18 of 18) sorted by relevance
| /u-boot/arch/arm/mach-sunxi/ |
| A D | dram_sun8i_a23.c | 42 .mr3 = 0,
119 writel(dram_para.mr3, &mctl_phy->mr3); in mctl_init()
203 writel((dram_para.mr2 << 16) | dram_para.mr3, &mctl_ctl->init4); in mctl_init()
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| A D | dram_sun8i_a83t.c | 139 writel(MCTL_MR3, &mctl_ctl->mr3); in auto_set_timing_para()
144 writel(MCTL_LPDDR3_MR3, &mctl_ctl->mr3); in auto_set_timing_para()
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| A D | dram_sun8i_a33.c | 138 writel(MCTL_MR3, &mctl_ctl->mr3); in auto_set_timing_para()
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| A D | dram_sun6i.c | 127 writel(MCTL_MR3, &mctl_phy->mr3); in mctl_channel_init()
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| A D | dram_sun9i.c | 637 writel(mr[3], &mctl_phy->mr3); in mctl_channel_init()
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| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| A D | dram_sun8i_a23.h | 27 u32 mr3; member
187 u32 mr3; /* 0x60 mode register 3 */ member
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| A D | dram_sun8i_a33.h | 81 u32 mr3; /* 0x3c */ member
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| A D | dram_sun8i_a83t.h | 81 u32 mr3; /* 0x3c */ member
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| A D | dram_sun9i.h | 114 u32 mr3; /* 0xa8 mode register 3 */ member
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| A D | dram_sun6i.h | 180 u32 mr3; /* 0x4c mode register 3 */ member
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| /u-boot/drivers/ram/stm32mp1/ |
| A D | stm32mp1_ddr.h | 140 u32 mr3; member
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| A D | stm32mp1_ddr_regs.h | 161 u32 mr3; /* 0x4C Mode 3*/ member
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| A D | stm32mp1_ddr.c | 178 DDRPHY_REG_TIMING(mr3),
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| /u-boot/arch/arm/mach-omap2/omap4/ |
| A D | sdram_elpida.c | 311 .mr3 = -1,
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| /u-boot/arch/arm/mach-omap2/omap5/ |
| A D | sdram.c | 443 .mr3 = 0x1,
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| /u-boot/doc/device-tree-bindings/clock/ |
| A D | rockchip,rk3288-dmc.txt | 92 mr0..mr3
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| /u-boot/arch/arm/mach-omap2/ |
| A D | emif-common.c | 127 if (mr_regs->mr3 > 0) in do_lpddr2_init()
128 set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3); in do_lpddr2_init()
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| /u-boot/arch/arm/include/asm/ |
| A D | emif.h | 1245 s8 mr3; member
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