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/u-boot/drivers/spi/
A Dmt7620_spi.c68 rate = DIV_ROUND_UP(ms->sys_freq, ms->speed); in mt7620_spi_master_setup()
103 writel(cfg, &ms->m[cs]->cfg); in mt7620_spi_master_setup()
113 if (ms->mode & SPI_CS_HIGH) in mt7620_spi_set_cs()
126 ms->mode = mode; in mt7620_spi_set_mode()
130 ms->mode |= SPI_MODE_3; in mt7620_spi_set_mode()
139 ms->speed = speed; in mt7620_spi_set_speed()
149 ms->wait_us); in mt7620_spi_busy_poll()
238 if (!ms->regs) in mt7620_spi_probe()
241 ms->m[0] = ms->regs + MT7620_SPI_MASTER1_OFF; in mt7620_spi_probe()
242 ms->m[1] = ms->regs + MT7620_SPI_MASTER2_OFF; in mt7620_spi_probe()
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/u-boot/doc/device-tree-bindings/i2c/
A Dgeneric-acpi.txt18 - reset-delay-ms : Delay after de-asserting reset, in ms
19 - reset-off-delay-ms : Delay after asserting reset (during power off)
20 - enable-delay-ms : Delay after asserting enable
21 - enable-off-delay-ms : Delay after de-asserting enable (during power off)
22 - stop-delay-ms : Delay after de-aserting stop
23 - stop-off-delay-ms : Delay after asserting stop (during power off)
38 reset-delay-ms = <20>;
40 enable-delay-ms = <1>;
/u-boot/doc/usage/
A Dload.rst51 149280 bytes read in 11 ms (12.9 MiB/s)
54 149280 bytes read in 9 ms (15.8 MiB/s)
57 149024 bytes read in 10 ms (14.2 MiB/s)
60 16 bytes read in 1 ms (15.6 KiB/s)
A Dbooti.rst52 27530 bytes read in 7 ms (3.7 MiB/s)
54 26990448 bytes read in 1175 ms (21.9 MiB/s)
56 27421776 bytes read in 1209 ms (21.6 MiB/s)
80 27530 bytes read in 6 ms (4.4 MiB/s)
82 9267730 bytes read in 402 ms (22 MiB/s)
84 27421776 bytes read in 1181 ms (22.1 MiB/s)
A Dbase.rst17 commands *cmp, cp, md, mdc, mm, ms, mw, mwc*.
/u-boot/arch/arm/dts/
A Dsun50i-a64-pine64-plus.dts30 * Ethernet PHY needs 30ms to properly power up and some more
31 * to initialize. 100ms should be plenty of time to finish
A Drk3399-gru-chromebook.dtsi120 * Need to wait 1ms + ramp-up time before we can power on WiFi.
121 * This has been approximated as 8ms total.
179 * 1ms after its regulators have ramped up (max rampup time is ~7ms).
266 realtek,dmic-init-delay-ms = <20>;
A Dsunxi-bananapi-m2-plus-v1.2.dtsi21 regulator-ramp-delay = <50>; /* 4ms */
A Dsun50i-h5-nanopi-neo-plus2.dts65 regulator-ramp-delay = <50>; /* 4ms */
74 post-power-on-delay-ms = <200>;
A Dstm32f429-disco.dts102 /* 1 ms panel driver settling time */
104 /* 5 ms touch detect interrupt delay */
A Dsun50i-a64-sopine-baseboard.dts127 * Ethernet PHY needs 30ms to properly power up and some more
128 * to initialize. 100ms should be plenty of time to finish
A Dsun50i-h5-emlid-neutis-n5-devboard.dts37 regulator-ramp-delay = <50>; /* 4ms */
A Dsun8i-h3-emlid-neutis-n5h3-devboard.dts26 regulator-ramp-delay = <50>; /* 4ms */
A Dsun8i-a23-polaroid-mid2809pxe04.dts60 /* The esp8089 needs 200 ms after driving wifi-en high */
61 post-power-on-delay-ms = <200>;
/u-boot/drivers/watchdog/
A Dmt7621_wdt.c40 static int mt762x_wdt_start(struct udevice *dev, u64 ms, ulong flags) in mt762x_wdt_start() argument
46 writel(ms, priv->regs + TIMER_REG_TMR1LOAD); in mt762x_wdt_start()
A Dmt7620_wdt.c48 static int mt7620_wdt_start(struct udevice *dev, u64 ms, ulong flags) in mt7620_wdt_start() argument
52 priv->timeout = ms; in mt7620_wdt_start()
A Darmada-37xx-wdt.c116 static int a37xx_wdt_start(struct udevice *dev, u64 ms, ulong flags) in a37xx_wdt_start() argument
130 priv->timeout = ms * priv->clk_rate / 1000 / CNTR_CTRL_PRESCALE_MIN; in a37xx_wdt_start()
/u-boot/doc/device-tree-bindings/video/
A Dintel-gma.txt15 - intel,panel-power-cycle-delay : T4 time sequence (6 = 500ms)
17 The following delays are in units of 0.1ms:
/u-boot/doc/device-tree-bindings/sound/
A Dda7219.txt49 - dlg,micbias-pulse-time : Mic bias higher voltage pulse duration (ms)
50 - dlg,btn-cfg : Periodic button press measurements for 4-pole jack (ms)
54 - dlg,jack-ins-deb : Debounce time for jack insertion (ms)
58 - dlg,jack-rem-deb : Debounce time for jack removal (ms)
A Dmax98357a.txt15 It's observed that 5ms is sufficient.
/u-boot/doc/device-tree-bindings/input/
A Dhid-over-i2c.txt30 - post-power-on-delay-ms
33 - post-power-on-delay-ms: time required by the device after enabling its regulators
/u-boot/doc/SPI/
A DREADME.ti_qspi_dra_test15 55872 bytes read in 8 ms (6.7 MiB/s)
18 248600 bytes read in 19 ms (12.5 MiB/s)
/u-boot/include/
A Dfsl_sec.h117 u32 ms; /* Job Ring LIODN Register, MS */ member
123 u32 ms; /* RTIC LIODN Register, MS */ member
129 u32 ms; /* DECO LIODN Register, MS */ member
/u-boot/arch/arm/cpu/armv7/sunxi/
A Dpsci.c62 static void __secure __mdelay(u32 ms) in __mdelay() argument
64 u32 reg = ONE_MS * ms; in __mdelay()
/u-boot/drivers/video/
A Dati_radeon_fb.h136 #define radeon_msleep(ms) _radeon_msleep(rinfo,ms) argument

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