Searched refs:mstr (Results 1 – 18 of 18) sorted by relevance
92 cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01041001; in cl_som_imx7_spl_dram_cfg_size()103 cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001; in cl_som_imx7_spl_dram_cfg_size()114 cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001; in cl_som_imx7_spl_dram_cfg_size()125 cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001; in cl_som_imx7_spl_dram_cfg_size()
60 writel(ddrc_regs_val->mstr, &ddrc_regs->mstr); in mx7_dram_cfg()144 reg_val = readl(&ddrc_regs->mstr); in imx_ddr_size()
213 writel(0x01040001, &mctl_ctl->mstr); in mctl_init()215 writel(0x01040401, &mctl_ctl->mstr); in mctl_init()251 setbits_le32(&mctl_ctl->mstr, 0x1000); in mctl_init()
598 &mctl_ctl->mstr); in mctl_channel_init()
323 writel(reg_val | BIT(31), &mctl_ctl->mstr); in mctl_com_init()
863 writel(BIT(31) | BIT(30) | reg_val, &mctl_ctl->mstr); in mctl_ctrl_init()
75 DDRCTL_REG_REG(mstr),681 switch (config->c_reg.mstr & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK) { in stm32mp1_ddr_init()694 if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3) in stm32mp1_ddr_init()696 else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR2) { in stm32mp1_ddr_init()701 } else if (config->c_reg.mstr & DDRCTRL_MSTR_LPDDR3) { in stm32mp1_ddr_init()795 if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3) in stm32mp1_ddr_init()
41 u32 mstr; member
12 u32 mstr ; /* 0x0 Master*/ member
69 u32 data_bus = readl(&ctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK; in get_nb_bytes()
940 switch (readl(&ctl->mstr) & DDRCTRL_MSTR_DATA_BUS_WIDTH_MASK) { in test_freq_pattern()
36 .mstr = 0x01040001,
19 u32 mstr; /* 0x0000 */ member
61 u32 mstr; /* 0x000 */ member
45 u32 mstr; /* 0x00 master register */ member
76 u32 mstr; /* 0x000 */ member
92 u32 mstr; /* 0x00 */ member
69 u32 mstr; member
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