Home
last modified time | relevance | path

Searched refs:mult (Results 1 – 25 of 49) sorted by relevance

12

/u-boot/drivers/clk/
A Dclk-fixed-factor.c27 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
38 unsigned int mult, unsigned int div) in clk_hw_register_fixed_factor() argument
49 fix->mult = mult; in clk_hw_register_fixed_factor()
66 unsigned int mult, unsigned int div) in clk_register_fixed_factor() argument
70 clk = clk_hw_register_fixed_factor(dev, name, parent_name, flags, mult, in clk_register_fixed_factor()
A Dclk_fixed_factor.c17 unsigned int mult; member
34 return rate * ff->mult; in clk_fixed_factor_get_rate()
52 ff->mult = dev_read_u32_default(dev, "clock-mult", 1); in clk_fixed_factor_of_to_plat()
/u-boot/cmd/
A Dsleep.c28 uint mult = CONFIG_SYS_HZ / 10; in do_sleep() local
29 for (frpart++; *frpart != '\0' && mult > 0; frpart++) { in do_sleep()
34 mdelay += (*frpart - '0') * mult; in do_sleep()
35 mult /= 10; in do_sleep()
/u-boot/arch/arm/dts/
A Domap36xx-omap3430es2plus-clocks.dtsi38 clock-mult = <1>;
54 clock-mult = <1>;
78 clock-mult = <1>;
86 clock-mult = <1>;
94 clock-mult = <1>;
102 clock-mult = <1>;
110 clock-mult = <1>;
118 clock-mult = <1>;
126 clock-mult = <1>;
134 clock-mult = <1>;
[all …]
A Dam33xx-clocks.dtsi23 clock-mult = <1>;
31 clock-mult = <1>;
39 clock-mult = <1>;
47 clock-mult = <1>;
55 clock-mult = <1>;
63 clock-mult = <1>;
71 clock-mult = <1>;
79 clock-mult = <1>;
87 clock-mult = <1>;
95 clock-mult = <1>;
[all …]
A Dam43xx-clocks.dtsi39 clock-mult = <1>;
47 clock-mult = <1>;
55 clock-mult = <1>;
63 clock-mult = <1>;
71 clock-mult = <1>;
79 clock-mult = <1>;
87 clock-mult = <1>;
95 clock-mult = <1>;
103 clock-mult = <1>;
321 clock-mult = <1>;
[all …]
A Domap36xx-clocks.dtsi74 clock-mult = <1>;
78 clock-mult = <1>;
82 ti,clock-mult = <1>;
86 ti,clock-mult = <1>;
90 clock-mult = <1>;
A Dkeystone-clocks.dtsi31 clock-mult = <1>;
40 clock-mult = <1>;
69 clock-mult = <1>;
78 clock-mult = <1>;
87 clock-mult = <1>;
96 clock-mult = <1>;
105 clock-mult = <1>;
114 clock-mult = <1>;
123 clock-mult = <1>;
132 clock-mult = <1>;
[all …]
A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi15 clock-mult = <1>;
23 clock-mult = <1>;
58 clock-mult = <1>;
66 clock-mult = <1>;
74 clock-mult = <1>;
82 clock-mult = <1>;
90 clock-mult = <1>;
A Domap3xxx-clocks.dtsi46 clock-mult = <2>;
54 clock-mult = <2>;
62 clock-mult = <2>;
70 clock-mult = <1>;
78 clock-mult = <1>;
216 clock-mult = <2>;
233 clock-mult = <1>;
258 clock-mult = <2>;
275 clock-mult = <1>;
305 clock-mult = <1>;
[all …]
A Domap54xx-clocks.dtsi128 clock-mult = <1>;
154 clock-mult = <1>;
201 clock-mult = <1>;
209 clock-mult = <1>;
298 clock-mult = <1>;
351 clock-mult = <1>;
375 clock-mult = <1>;
383 clock-mult = <1>;
401 clock-mult = <1>;
481 clock-mult = <1>;
[all …]
A Ddra7xx-clocks.dtsi111 clock-mult = <1>;
290 clock-mult = <1>;
316 clock-mult = <1>;
324 clock-mult = <1>;
362 clock-mult = <1>;
400 clock-mult = <1>;
449 clock-mult = <1>;
509 clock-mult = <1>;
517 clock-mult = <1>;
525 clock-mult = <1>;
[all …]
A Domap34xx-omap36xx-clocks.dtsi15 clock-mult = <1>;
80 clock-mult = <1>;
128 clock-mult = <1>;
152 clock-mult = <1>;
A Domap44xx-clocks.dtsi161 clock-mult = <1>;
233 clock-mult = <1>;
289 clock-mult = <1>;
407 clock-mult = <1>;
415 clock-mult = <1>;
441 clock-mult = <1>;
449 clock-mult = <1>;
466 clock-mult = <1>;
505 clock-mult = <1>;
705 clock-mult = <1>;
[all …]
/u-boot/drivers/clk/renesas/
A Dclk-rcar-gen3.c166 u32 value, mult, div, prediv, postdiv; in gen3_clk_get_rate64() local
216 mult = (((value >> 24) & 0x7f) + 1) * 2; in gen3_clk_get_rate64()
217 rate = gen3_clk_get_rate64(&parent) * mult; in gen3_clk_get_rate64()
219 __func__, __LINE__, core->parent, mult, rate); in gen3_clk_get_rate64()
233 mult = (((value >> 24) & 0x7f) + 1) * 2; in gen3_clk_get_rate64()
234 rate = gen3_clk_get_rate64(&parent) * mult; in gen3_clk_get_rate64()
236 __func__, __LINE__, core->parent, mult, rate); in gen3_clk_get_rate64()
250 mult = (((value >> 24) & 0x7f) + 1) * 2; in gen3_clk_get_rate64()
251 rate = gen3_clk_get_rate64(&parent) * mult; in gen3_clk_get_rate64()
253 __func__, __LINE__, core->parent, mult, rate); in gen3_clk_get_rate64()
[all …]
A Drenesas-cpg-mssr.h51 unsigned int mult; member
75 DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
79 DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
81 DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
A Dclk-rcar-gen2.c84 u32 value, mult, div, rate = 0; in gen2_clk_get_rate() local
125 rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div; in gen2_clk_get_rate()
128 core->parent, core->mult, core->div, rate); in gen2_clk_get_rate()
153 mult = pll_config->pll0_mult; in gen2_clk_get_rate()
154 if (!mult) { in gen2_clk_get_rate()
156 mult = (((value >> 24) & 0x7f) + 1) * 2; in gen2_clk_get_rate()
159 rate = (gen2_clk_get_rate(&parent) * mult) / info->pll0_div; in gen2_clk_get_rate()
161 __func__, __LINE__, core->parent, mult, rate); in gen2_clk_get_rate()
/u-boot/drivers/clk/mvebu/
A Darmada-37xx-tbg.c57 unsigned int mult[NUM_TBG]; member
128 unsigned int mult, div; in armada_37xx_tbg_clk_probe() local
130 mult = tbg_get_mult(reg, &tbg[i]); in armada_37xx_tbg_clk_probe()
133 priv->rates[i] = (xtal * mult) / div; in armada_37xx_tbg_clk_probe()
/u-boot/doc/device-tree-bindings/clock/
A Dfixed-factor-clock.txt11 - clock-mult: fixed multiplier.
23 clock-mult = <1>;
/u-boot/arch/arm/mach-keystone/
A Dclock.c70 pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK); in configure_mult_div()
282 unsigned long mult = 1, prediv = 1, output_div = 2; in pll_freq_get() local
292 mult = ((tmp & CFG_PLLCTL0_PLLM_HI_MASK) >> in pll_freq_get()
294 (pllctl_reg_read(pll, mult) & in pll_freq_get()
300 ret = ret / prediv / output_div * mult; in pll_freq_get()
333 mult = ((tmp & CFG_PLLCTL0_PLLM_MASK) >> in pll_freq_get()
337 ret = ((ret / prediv) * mult) / output_div; in pll_freq_get()
/u-boot/include/
A Dsandbox-clk.h37 unsigned int mult, in sandbox_clk_fixed_factor() argument
41 CLK_SET_RATE_PARENT, mult, div); in sandbox_clk_fixed_factor()
/u-boot/drivers/clk/ti/
A Dclk-am3-dpll.c41 int mult = INT_MAX, div = INT_MAX; in clk_ti_am3_dpll_round_rate() local
60 mult = m; in clk_ti_am3_dpll_round_rate()
71 priv->last_rounded_mult = mult; in clk_ti_am3_dpll_round_rate()
74 ret, mult, div); in clk_ti_am3_dpll_round_rate()
/u-boot/drivers/clk/mediatek/
A Dclk-mtk.h80 u32 mult; member
88 .mult = _mult, \
/u-boot/arch/arm/mach-imx/mx7ulp/
A Dscg.c481 u32 reg, pre_div, infreq, mult; in decode_pll() local
501 mult = (reg & SCG1_SPLL_CFG_MULT_MASK) >> in decode_pll()
517 return infreq * mult + infreq * num / denom; in decode_pll()
519 return infreq * mult; in decode_pll()
533 mult = (reg & SCG_APLL_CFG_MULT_MASK) >> in decode_pll()
549 return infreq * mult + infreq * num / denom; in decode_pll()
551 return infreq * mult; in decode_pll()
/u-boot/include/linux/
A Dclk-provider.h191 unsigned int mult; member
232 unsigned int mult, unsigned int div);

Completed in 43 milliseconds

12