Home
last modified time | relevance | path

Searched refs:mv_ddr_freq_get (Results 1 – 6 of 6) sorted by relevance

/u-boot/drivers/ddr/marvell/a38x/
A Dmv_ddr_training_db.h34 u32 mv_ddr_freq_get(enum mv_ddr_freq freq);
A Dmv_ddr_topology.c108 tclk = 1000000 / mv_ddr_freq_get(iface_params->memory_freq); in mv_ddr_topology_map_update()
A Dddr3_training.c392 t_ckclk = (MEGA / mv_ddr_freq_get(freq)); in hws_ddr3_tip_init_controller()
669 adll_tap = MEGA / (mv_ddr_freq_get(freq) * 64); in hws_ddr3_tip_init_controller()
1174 mdelay(100 / (mv_ddr_freq_get(frequency)) / mv_ddr_freq_get(MV_DDR_FREQ_LOW_FREQ)); in adll_calibration()
1219 u32 freq = mv_ddr_freq_get(frequency); in ddr3_tip_freq_set()
1458 mdelay(100 / (freq / mv_ddr_freq_get(MV_DDR_FREQ_LOW_FREQ))); in ddr3_tip_freq_set()
1636 u32 freq = mv_ddr_freq_get(frequency); in ddr3_tip_set_timing()
A Dddr3_training_db.c53 u32 mv_ddr_freq_get(enum mv_ddr_freq freq) in mv_ddr_freq_get() function
A Dmv_ddr_plat.c383 if ((frequency == MV_DDR_FREQ_LOW_FREQ) || (mv_ddr_freq_get(frequency) <= 400)) in ddr3_tip_clock_mode()
737 u32 freq = mv_ddr_freq_get(frequency); in ddr3_tip_a38x_set_divider()
A Dddr3_training_pbs.c39 int adll_tap = MEGA / mv_ddr_freq_get(medium_freq) / 64; in ddr3_tip_pbs()

Completed in 13 milliseconds