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/u-boot/include/linux/
A Dlog2.h27 int __ilog2_u32(u32 n) in __ilog2_u32() argument
29 return fls(n) - 1; in __ilog2_u32()
35 int __ilog2_u64(u64 n) in __ilog2_u64() argument
37 return fls64(n) - 1; in __ilog2_u64()
52 return (n != 0 && ((n & (n - 1)) == 0)); in is_power_of_2()
85 #define ilog2(n) \ argument
88 (n) < 2 ? 0 : \
154 __ilog2_u64(n) \
168 (n == 1) ? 1 : \
192 return n > 1 ? ilog2(n - 1) + 1 : 0; in __order_base_2()
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/u-boot/tools/omap/
A Dclocks_get_m_n.c53 u32 m, n; in get_m_n_optimized() local
54 n = 1; in get_m_n_optimized()
59 freq = ref_freq_khz * 2 * m / n; in get_m_n_optimized()
71 n_optimal = n; in get_m_n_optimized()
73 n++; in get_m_n_optimized()
75 ((ref_freq_khz / n) < 1000)) { in get_m_n_optimized()
79 n--; in get_m_n_optimized()
89 u32 m, n; in main() local
91 get_m_n_optimized(2000000, 12000, &m, &n); in main()
92 get_m_n_optimized(2000000, 13000, &m, &n); in main()
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/u-boot/arch/mips/mach-jz47xx/include/mach/
A Djz4780.h36 #define GPIO_PXPIN(n) (0x00 + (n) * 0x100) argument
37 #define GPIO_PXINT(n) (0x10 + (n) * 0x100) argument
38 #define GPIO_PXINTS(n) (0x14 + (n) * 0x100) argument
39 #define GPIO_PXINTC(n) (0x18 + (n) * 0x100) argument
40 #define GPIO_PXMASK(n) (0x20 + (n) * 0x100) argument
41 #define GPIO_PXMASKS(n) (0x24 + (n) * 0x100) argument
43 #define GPIO_PXPAT1(n) (0x30 + (n) * 0x100) argument
46 #define GPIO_PXPAT0(n) (0x40 + (n) * 0x100) argument
49 #define GPIO_PXFLG(n) (0x50 + (n) * 0x100) argument
51 #define GPIO_PXOEN(n) (0x60 + (n) * 0x100) argument
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/u-boot/arch/arm/include/asm/arch-sunxi/
A Dprcm_sun6i.h15 #define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4) argument
17 #define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1) argument
20 #define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8) argument
22 #define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1) argument
25 #define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16) argument
40 #define __PRCM_APB0_RATIO(n) (((n) & 0x3) << 0) argument
42 #define __PRCM_APB0_RATIO_DIV(n) (((n) >> 1) - 1) argument
126 #define __PRCM_CLK_MOD0_M(n) (((n) & 0xf) << 0) argument
128 #define __PRCM_CLK_MOD0_M_X(n) (n - 1) argument
132 #define _PRCM_CLK_MOD0_N(n) (((n) & 0x3) << 16) argument
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A Dp2wi.h24 #define __P2WI_CC_CLK(n) (((n) & 0xff) << 0) argument
26 #define __P2WI_CC_CLK_DIV(n) (((n) >> 1) - 1) argument
29 #define P2WI_CC_SDA_OUT_DELAY(n) (((n) & 0x7) << 8) argument
39 #define __P2WI_STAT_TRANS_ERR(n) (((n) & 0xff) << 8) argument
88 #define P2WI_DATA_BYTE_1(n) (((n) & 0xff) << 0) argument
90 #define P2WI_DATA_BYTE_2(n) (((n) & 0xff) << 8) argument
92 #define P2WI_DATA_BYTE_3(n) (((n) & 0xff) << 16) argument
94 #define P2WI_DATA_BYTE_4(n) (((n) & 0xff) << 24) argument
96 #define P2WI_DATA_BYTE_5(n) (((n) & 0xff) << 0) argument
98 #define P2WI_DATA_BYTE_6(n) (((n) & 0xff) << 8) argument
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A Ddram_sun4i.h107 #define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1) argument
111 #define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3) argument
119 #define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6) argument
124 #define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10) argument
127 #define DRAM_DCR_MODE(n) (((n) & 0x3) << 13) argument
136 #define DRAM_DRR_TRFC(n) ((n) & 0xff) argument
137 #define DRAM_DRR_TREFI(n) (((n) & 0xffff) << 8) argument
140 #define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0) argument
142 #define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2) argument
152 #define DRAM_MCR_MODE_EN(n) (((n) & 0x3) << 13) argument
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A Dclock_sun4i.h216 #define CCM_PLL5_CTRL_M(n) (((n) & 0x3) << 0) argument
218 #define CCM_PLL5_CTRL_M_X(n) ((n) - 1) argument
221 #define CCM_PLL5_CTRL_M1_X(n) ((n) - 1) argument
222 #define CCM_PLL5_CTRL_K(n) (((n) & 0x3) << 4) argument
225 #define CCM_PLL5_CTRL_K_X(n) ((n) - 1) argument
230 #define CCM_PLL5_CTRL_N_X(n) (n) argument
234 #define CCM_PLL5_CTRL_P_X(n) ((n) - 1) argument
239 #define CCM_PLL5_CTRL_BIAS_X(n) ((n) - 1) argument
258 #define CCM_MBUS_CTRL_M(n) (((n) & 0xf) << 0) argument
260 #define CCM_MBUS_CTRL_M_X(n) ((n) - 1) argument
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A Dlcdc.h78 #define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) argument
80 #define SUNXI_LCDC_TCON0_DCLK_DIV(n) ((n) << 0) argument
82 #define SUNXI_LCDC_TCON0_TIMING_H_BP(n) (((n) - 1) << 0) argument
83 #define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16) argument
84 #define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0) argument
85 #define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16) argument
91 #define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26) argument
97 #define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0) argument
98 #define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16) argument
99 #define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0) argument
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/u-boot/arch/arm/include/asm/arch-lpc32xx/
A Dtimer.h28 #define TIMER_IR_CR(n) (1 << ((n) + 4)) argument
29 #define TIMER_IR_MR(n) (1 << (n)) argument
37 #define TIMER_MCR_STOP(n) (1 << (3 * (n) + 2)) argument
38 #define TIMER_MCR_RESET(n) (1 << (3 * (n) + 1)) argument
39 #define TIMER_MCR_INTERRUPT(n) (1 << (3 * (n))) argument
42 #define TIMER_CCR_INTERRUPT(n) (1 << (3 * (n) + 2)) argument
43 #define TIMER_CCR_FALLING_EDGE(n) (1 << (3 * (n) + 1)) argument
44 #define TIMER_CCR_RISING_EDGE(n) (1 << (3 * (n))) argument
48 #define TIMER_EMR_EMC_SET(n) (0x2 << (2 * (n) + 4)) argument
51 #define TIMER_EMR_EM(n) (1 << (n)) argument
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/u-boot/arch/arm/include/asm/arch-rockchip/
A Dsdram_px30.h19 #define PMUGRF_OS_REG(n) (PMUGRF_OS_REG0 + (n) * 4) argument
22 #define DDR_GRF_CON(n) (0 + (n) * 4) argument
24 #define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4) argument
42 #define PB(n) ((0x1 << (15 + 16)) | ((n) << 15)) argument
44 #define FBDIV(n) ((0xFFF << 16) | (n)) argument
48 #define RST(n) ((0x1 << (14 + 16)) | ((n) << 14)) argument
49 #define PD(n) ((0x1 << (13 + 16)) | ((n) << 13)) argument
50 #define DSMPD(n) ((0x1 << (12 + 16)) | ((n) << 12)) argument
51 #define LOCK(n) (((n) >> 10) & 0x1) argument
52 #define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6)) argument
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A Dsdram_rk3328.h34 #define DDR_GRF_CON(n) (0 + (n) * 4) argument
36 #define DDR_GRF_STATUS(n) (DDR_GRF_STATUS_BASE + (n) * 4) argument
62 #define PB(n) ((0x1 << (15 + 16)) | ((n) << 15)) argument
63 #define POSTDIV1(n) ((0x7 << (12 + 16)) | ((n) << 12)) argument
64 #define FBDIV(n) ((0xFFF << 16) | (n)) argument
67 #define RSTMODE(n) ((0x1 << (15 + 16)) | ((n) << 15)) argument
68 #define RST(n) ((0x1 << (14 + 16)) | ((n) << 14)) argument
69 #define PD(n) ((0x1 << (13 + 16)) | ((n) << 13)) argument
71 #define LOCK(n) (((n) >> 10) & 0x1) argument
72 #define POSTDIV2(n) ((0x7 << (6 + 16)) | ((n) << 6)) argument
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A Dsdram_common.h71 #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch))) argument
72 #define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1) argument
74 #define SYS_REG_ENC_DDRTYPE(n) ((n) << 13) argument
75 #define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7) argument
76 #define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12) argument
77 #define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1)) argument
80 #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + ((ch) * 16))) argument
82 #define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << \ argument
85 #define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + ((ch) * 16))) argument
90 #define SYS_REG_ENC_VERSION(n) ((n) << 28) argument
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/u-boot/arch/x86/cpu/qemu/
A De820.c22 int n = 0; in install_e820_map() local
24 entries[n].addr = 0; in install_e820_map()
26 entries[n].type = E820_RAM; in install_e820_map()
27 n++; in install_e820_map()
32 n++; in install_e820_map()
42 n++; in install_e820_map()
48 n++; in install_e820_map()
53 n++; in install_e820_map()
58 n++; in install_e820_map()
65 n++; in install_e820_map()
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/u-boot/arch/arm/mach-snapdragon/include/mach/
A Dsysmap-apq8016.h18 #define SDCC_BCR(n) ((n * 0x1000) + 0x41000) argument
19 #define SDCC_CMD_RCGR(n) ((n * 0x1000) + 0x41004) argument
20 #define SDCC_CFG_RCGR(n) ((n * 0x1000) + 0x41008) argument
21 #define SDCC_M(n) ((n * 0x1000) + 0x4100C) argument
22 #define SDCC_N(n) ((n * 0x1000) + 0x41010) argument
23 #define SDCC_D(n) ((n * 0x1000) + 0x41014) argument
24 #define SDCC_APPS_CBCR(n) ((n * 0x1000) + 0x41018) argument
25 #define SDCC_AHB_CBCR(n) ((n * 0x1000) + 0x4101C) argument
/u-boot/drivers/usb/dwc3/
A Dcore.h114 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10)) argument
130 #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10)) argument
142 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19) argument
151 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12) argument
158 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4) argument
177 #define DWC3_GUSB2PHYCFG_PHYIF(n) ((n) << 3) argument
255 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24) argument
261 #define DWC3_DCTL_TRGTULST(n) ((n) << 17) argument
386 #define DWC3_DALEPENA_EP(n) (1 << n) argument
597 #define DWC3_MODE(n) ((n) & 0x7) argument
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/u-boot/include/
A Dfm_eth.h82 .num = n - 1, \
84 .port = FM##idx##_DTSEC##n, \
96 .num = n - 1, \
98 .port = FM##idx##_10GEC##n, \
110 .num = n - 1, \
112 .port = FM##idx##_10GEC##n, \
123 .num = n - 1, \
125 .port = FM##idx##_10GEC##n, \
139 .num = n - 1, \
154 .num = n - 1, \
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A Dfsl_ifc.h203 #define FTIM0_NAND_TWP(n) ((n) << FTIM0_NAND_TWP_SHIFT) argument
207 #define FTIM0_NAND_TWH(n) ((n) << FTIM0_NAND_TWH_SHIFT) argument
217 #define FTIM1_NAND_TRR(n) ((n) << FTIM1_NAND_TRR_SHIFT) argument
219 #define FTIM1_NAND_TRP(n) ((n) << FTIM1_NAND_TRP_SHIFT) argument
235 #define FTIM3_NAND_TWW(n) ((n) << FTIM3_NAND_TWW_SHIFT) argument
254 #define FTIM1_NOR_TACO(n) ((n) << FTIM1_NOR_TACO_SHIFT) argument
264 #define FTIM2_NOR_TCS(n) ((n) << FTIM2_NOR_TCS_SHIFT) argument
266 #define FTIM2_NOR_TCH(n) ((n) << FTIM2_NOR_TCH_SHIFT) argument
268 #define FTIM2_NOR_TWPH(n) ((n) << FTIM2_NOR_TWPH_SHIFT) argument
270 #define FTIM2_NOR_TWP(n) ((n) << FTIM2_NOR_TWP_SHIFT) argument
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/u-boot/drivers/phy/rockchip/
A Dphy-rockchip-typec.c118 #define XCVR_PSM_RCTRL(n) ((0x4001 | ((n) << 9)) << 2) argument
146 #define TX_PSC_A0(n) ((0x4100 | ((n) << 9)) << 2) argument
147 #define TX_PSC_A1(n) ((0x4101 | ((n) << 9)) << 2) argument
148 #define TX_PSC_A2(n) ((0x4102 | ((n) << 9)) << 2) argument
149 #define TX_PSC_A3(n) ((0x4103 | ((n) << 9)) << 2) argument
217 #define RX_PSC_A0(n) ((0x8000 | ((n) << 9)) << 2) argument
218 #define RX_PSC_A1(n) ((0x8001 | ((n) << 9)) << 2) argument
219 #define RX_PSC_A2(n) ((0x8002 | ((n) << 9)) << 2) argument
220 #define RX_PSC_A3(n) ((0x8003 | ((n) << 9)) << 2) argument
221 #define RX_PSC_CAL(n) ((0x8006 | ((n) << 9)) << 2) argument
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/u-boot/drivers/firmware/scmi/
A Dsandbox-scmi_devices.c53 size_t n; in sandbox_scmi_devices_remove() local
58 for (n = 0; n < SCMI_TEST_DEVICES_RD_COUNT; n++) { in sandbox_scmi_devices_remove()
59 int ret2 = reset_free(devices->reset + n); in sandbox_scmi_devices_remove()
72 size_t n; in sandbox_scmi_devices_probe() local
81 for (n = 0; n < SCMI_TEST_DEVICES_CLK_COUNT; n++) { in sandbox_scmi_devices_probe()
82 ret = clk_get_by_index(dev, n, priv->devices.clk + n); in sandbox_scmi_devices_probe()
84 dev_err(dev, "%s: Failed on clk %zu\n", __func__, n); in sandbox_scmi_devices_probe()
89 for (n = 0; n < SCMI_TEST_DEVICES_RD_COUNT; n++) { in sandbox_scmi_devices_probe()
90 ret = reset_get_by_index(dev, n, priv->devices.reset + n); in sandbox_scmi_devices_probe()
100 for (; n > 0; n--) in sandbox_scmi_devices_probe()
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/u-boot/arch/arm/include/asm/ti-common/
A Ddavinci_nand.h77 #define DAVINCI_NANDFCR_NAND_ENABLE(n) (1 << ((n) - 2)) argument
79 #define DAVINCI_NANDFCR_4BIT_ECC_SEL(n) (((n) - 2) << 4) argument
80 #define DAVINCI_NANDFCR_1BIT_ECC_START(n) (1 << (8 + ((n) - 2))) argument
88 #define DAVINCI_ABCR_WSETUP(n) (n << 26) argument
89 #define DAVINCI_ABCR_WSTROBE(n) (n << 20) argument
90 #define DAVINCI_ABCR_WHOLD(n) (n << 17) argument
91 #define DAVINCI_ABCR_RSETUP(n) (n << 13) argument
92 #define DAVINCI_ABCR_RSTROBE(n) (n << 7) argument
93 #define DAVINCI_ABCR_RHOLD(n) (n << 4) argument
94 #define DAVINCI_ABCR_TA(n) (n << 2) argument
/u-boot/fs/btrfs/
A Dconv-funcs.h29 static inline struct n *n##_to_disk(struct n * r) \
33 static inline struct n *n##_to_cpu(struct n * r) \
39 static inline struct n *n##_to_disk_##a(struct n * r) \
43 static inline struct n *n##_to_cpu_##a(struct n * r) \
60 static inline struct n * n##_to_disk(struct n *); \
61 static inline struct n * n##_to_cpu(struct n *); \
62 static inline struct n n##_to_disk_v(struct n x) { \
65 static inline struct n n##_to_cpu_v(struct n x) { \
111 DEFINE_CONV_ONE(n,n##_to_disk,DEFINE_CONV_CPU_TO_LE,##__VA_ARGS__) \
112 DEFINE_CONV_ONE(n,n##_to_cpu,DEFINE_CONV_LE_TO_CPU,##__VA_ARGS__)
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/u-boot/lib/efi_loader/
A Defi_freestanding.c23 int memcmp(const void *s1, const void *s2, size_t n) in memcmp() argument
28 for (; n; --n) { in memcmp()
45 void *memmove(void *dest, const void *src, size_t n) in memmove() argument
51 for (; n; --n) in memmove()
54 d += n; in memmove()
55 s += n; in memmove()
56 for (; n; --n) in memmove()
70 void *memcpy(void *dest, const void *src, size_t n) in memcpy() argument
72 return memmove(dest, src, n); in memcpy()
83 void *memset(void *s, int c, size_t n) in memset() argument
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/u-boot/drivers/clk/at91/
A Dsam9x60.c180 const char *n; member
190 .n = "plla_fracck",
201 .n = "plla_divpmcck",
212 .n = "upll_fracck",
223 .n = "upll_divpmcck",
240 const char *n; member
258 const char *n; member
275 const char *n; member
278 { .n = "pioA_clk", .id = 2, },
336 const char *n; member
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A Dsama7g5.c232 const char *n; member
396 const char *n; member
406 .n = "mck1",
417 .n = "mck2",
428 .n = "mck3",
438 .n = "mck4",
455 const char *n; member
479 const char *n; member
502 const char *n; member
593 const char *n; member
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/u-boot/tools/
A Dgetline.c28 if (!lineptr || !n || !stream) in getstr()
32 *n = MIN_CHUNK; in getstr()
33 *lineptr = malloc(*n); in getstr()
38 nchars_avail = *n - offset; in getstr()
50 if (*n > MIN_CHUNK) in getstr()
51 *n *= 2; in getstr()
53 *n += MIN_CHUNK; in getstr()
55 nchars_avail = *n + *lineptr - read_pos; in getstr()
56 *lineptr = realloc(*lineptr, *n); in getstr()
59 read_pos = *n - nchars_avail + *lineptr; in getstr()
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