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Searched refs:nint (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/mips/mach-ath79/ar934x/
A Dclk.c40 u8 nint[2]; member
149 pll_nint = pll_cfg->nint[xtal_40]; in ar934x_pll_init()
158 pll_nint = pll_cfg->nint[xtal_40]; in ar934x_pll_init()
240 const u32 nint = (regval >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & in ar934x_cpupll_to_hz() local
246 return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv)); in ar934x_cpupll_to_hz()
255 const u32 nint = (regval >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & in ar934x_ddrpll_to_hz() local
261 return (xtal * (nint + (nfrac >> 9))) / (refdiv * (1 << outdiv)); in ar934x_ddrpll_to_hz()
/u-boot/arch/mips/mach-ath79/qca953x/
A Dlowlevel_init.S37 #define MK_PLL_CPU_CONF(frac, nint, ref, outdiv) \ argument
39 PLL_CPU_NINT(nint) | \
47 #define MK_PLL_DDR_CONF(frac, nint, ref, outdiv) \ argument
50 PLL_DDR_NINT(nint) | \
/u-boot/arch/mips/mach-ath79/qca956x/
A Dclk.c314 u32 out_div, ref_div, postdiv, nint, hfrac, lfrac, clk_ctrl; in get_clocks() local
336 nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) & in get_clocks()
345 cpu_pll = nint * ref_rate / ref_div; in get_clocks()
356 nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) & in get_clocks()
363 ddr_pll = nint * ref_rate / ref_div; in get_clocks()

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