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Searched refs:num_of_total_pups (Results 1 – 5 of 5) sorted by relevance

/u-boot/drivers/ddr/marvell/axp/
A Dddr3_write_leveling.c111 pup < dram_info->num_of_total_pups; in ddr3_write_leveling_hw()
140 pup < dram_info->num_of_total_pups; in ddr3_write_leveling_hw()
434 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) { in ddr3_wl_supplement()
490 for (pup = 0; pup <= dram_info->num_of_total_pups; pup++) { in ddr3_write_leveling_hw_reg_dimm()
534 pup < dram_info->num_of_total_pups; in ddr3_write_leveling_hw_reg_dimm()
578 pup < dram_info->num_of_total_pups; in ddr3_write_leveling_hw_reg_dimm()
610 for (pup = 0; pup <= dram_info->num_of_total_pups; in ddr3_write_leveling_hw_reg_dimm()
623 pup < dram_info->num_of_total_pups; in ddr3_write_leveling_hw_reg_dimm()
639 for (pup = 0; pup <= dram_info->num_of_total_pups; in ddr3_write_leveling_hw_reg_dimm()
663 max_pup_num = dram_info->num_of_total_pups; in ddr3_write_leveling_sw()
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A Dddr3_pbs.c105 pups = dram_info->num_of_total_pups; in ddr3_pbs_tx()
106 max_pup = dram_info->num_of_total_pups; in ddr3_pbs_tx()
548 pups = dram_info->num_of_total_pups; in ddr3_pbs_rx()
549 max_pup = dram_info->num_of_total_pups; in ddr3_pbs_rx()
1425 max_pup = dram_info->num_of_total_pups; in ddr3_set_pbs_results()
A Dddr3_read_leveling.c101 pup < dram_info->num_of_total_pups; in ddr3_read_leveling_hw()
132 pup < (dram_info->num_of_total_pups); in ddr3_read_leveling_hw()
731 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) { in ddr3_read_leveling_single_cs_rl_mode()
1206 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) { in ddr3_read_leveling_single_cs_window_mode()
A Dddr3_hw_training.c122 dram_info.num_of_total_pups = ddr_width / PUP_SIZE + dram_info.ecc_ena; in ddr3_hw_training()
720 for (pup = 0; pup < dram_info->num_of_total_pups; in ddr3_save_training()
1055 for (pup = 0; pup < dram_info->num_of_total_pups; pup++) { in ddr3_get_min_max_rl_phase()
A Dddr3_hw_training.h255 u32 num_of_total_pups; /* numOfStdPups + eccEna */ member

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