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Searched refs:num_parents (Results 1 – 25 of 29) sorted by relevance

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/u-boot/drivers/clk/
A Dclk-mux.c43 int num_parents = mux->num_parents; in clk_mux_val_to_index() local
48 for (i = 0; i < num_parents; i++) in clk_mux_val_to_index()
60 if (val >= num_parents) in clk_mux_val_to_index()
109 for (i = 0; i < mux->num_parents; i++) { in clk_fetch_parent_index()
159 const char * const *parent_names, u8 num_parents, in clk_hw_register_mux_table() argument
184 mux->num_parents = num_parents; in clk_hw_register_mux_table()
216 const char * const *parent_names, u8 num_parents, in clk_register_mux_table() argument
223 clk = clk_hw_register_mux_table(dev, name, parent_names, num_parents, in clk_register_mux_table()
232 const char * const *parent_names, u8 num_parents, in clk_register_mux() argument
239 return clk_register_mux_table(dev, name, parent_names, num_parents, in clk_register_mux()
A Dclk_sandbox_ccf.c171 int num_parents, void __iomem *reg, in sandbox_clk_composite() argument
186 mux->num_parents = num_parents; in sandbox_clk_composite()
208 parent_names, num_parents, in sandbox_clk_composite()
A Dclk-composite.c100 int num_parents, struct clk *mux, in clk_register_composite() argument
112 if (!num_parents || (num_parents != 1 && !mux)) in clk_register_composite()
A Dclk_versal.c95 u32 num_parents; member
325 u32 *num_parents) in versal_clock_get_parents() argument
330 *num_parents = 0; in versal_clock_get_parents()
339 num_parents); in versal_clock_get_parents()
343 } while (*num_parents <= MAX_PARENT); in versal_clock_get_parents()
599 &clock[i].num_parents); in versal_get_clock_info()
A Dclk-uclass.c213 int num_parents; in clk_set_default_parents() local
216 num_parents = dev_count_phandle_with_args(dev, "assigned-clock-parents", in clk_set_default_parents()
218 if (num_parents < 0) { in clk_set_default_parents()
224 for (index = 0; index < num_parents; index++) { in clk_set_default_parents()
/u-boot/drivers/clk/at91/
A Dsckc.c27 unsigned int num_parents; member
56 for (i = 0; i < sckc->num_parents; i++) { in sam9x60_td_slck_set_parent()
60 if (i == sckc->num_parents) in sam9x60_td_slck_set_parent()
75 int num_parents) in at91_sam9x60_clk_register_td_slck() argument
81 if (!sckc || !name || !parent_names || num_parents != 2) in at91_sam9x60_clk_register_td_slck()
84 sckc->parent_names = kzalloc(sizeof(*sckc->parent_names) * num_parents, in at91_sam9x60_clk_register_td_slck()
89 for (i = 0; i < num_parents; i++) { in at91_sam9x60_clk_register_td_slck()
95 sckc->num_parents = num_parents; in at91_sam9x60_clk_register_td_slck()
A Dpmc.c138 int at91_clk_mux_val_to_index(const u32 *table, u32 num_parents, u32 val) in at91_clk_mux_val_to_index() argument
142 if (!table || !num_parents) in at91_clk_mux_val_to_index()
145 for (i = 0; i < num_parents; i++) { in at91_clk_mux_val_to_index()
163 int at91_clk_mux_index_to_val(const u32 *table, u32 num_parents, u32 index) in at91_clk_mux_index_to_val() argument
165 if (!table || !num_parents || index < 0 || index > num_parents) in at91_clk_mux_index_to_val()
A Dclk-master.c47 u32 num_parents; member
117 int num_parents, const struct clk_master_layout *layout, in at91_clk_register_master() argument
126 if (!base || !name || !num_parents || !parent_names || in at91_clk_register_master()
137 master->num_parents = num_parents; in at91_clk_register_master()
166 master->num_parents, parent->id); in clk_sama7g5_master_set_parent()
171 master->num_parents, index); in clk_sama7g5_master_set_parent()
269 int num_parents, const u32 *mux_table, const u32 *clk_mux_table, in at91_clk_sama7g5_register_master() argument
277 if (!base || !name || !num_parents || !parent_names || in at91_clk_sama7g5_register_master()
289 master->num_parents = num_parents; in at91_clk_sama7g5_register_master()
295 master->num_parents, in at91_clk_sama7g5_register_master()
A Dpmc.h87 const char * const *parent_names, int num_parents,
101 const char * const *parent_names, int num_parents,
107 const char * const *parent_names, int num_parents,
118 const char * const *parent_names, u8 num_parents, u8 id,
137 u8 num_parents, u8 id, const struct clk_range *range);
139 int at91_clk_mux_val_to_index(const u32 *table, u32 num_parents, u32 val);
140 int at91_clk_mux_index_to_val(const u32 *table, u32 num_parents, u32 index);
A Dclk-programmable.c32 u32 num_parents; member
64 prog->num_parents, parent->id); in clk_programmable_set_parent()
68 index = at91_clk_mux_index_to_val(prog->mux_table, prog->num_parents, in clk_programmable_set_parent()
131 const char *const *parent_names, u8 num_parents, u8 id, in at91_clk_register_programmable() argument
140 if (!base || !name || !parent_names || !num_parents || in at91_clk_register_programmable()
153 prog->num_parents = num_parents; in at91_clk_register_programmable()
161 prog->num_parents, val); in at91_clk_register_programmable()
A Dclk-generic.c31 u32 num_parents; member
68 index = at91_clk_mux_val_to_index(gck->clk_mux_table, gck->num_parents, in clk_gck_set_parent()
73 index = at91_clk_mux_index_to_val(gck->mux_table, gck->num_parents, in clk_gck_set_parent()
146 u8 num_parents, u8 id, in at91_clk_register_generic() argument
154 if (!base || !layout || !name || !parent_names || !num_parents || in at91_clk_register_generic()
168 gck->num_parents = num_parents; in at91_clk_register_generic()
180 index = at91_clk_mux_val_to_index(gck->mux_table, gck->num_parents, in at91_clk_register_generic()
A Dclk-main.c53 unsigned int num_parents; member
322 main->num_parents, AT91_CLK_ID_TO_DID(parent->id)); in clk_sam9x5_main_set_parent()
349 int num_parents, const u32 *clk_mux_table, in at91_clk_sam9x5_main() argument
357 if (!reg || !name || !parent_names || !num_parents || !clk_mux_table) in at91_clk_sam9x5_main()
366 main->num_parents = num_parents; in at91_clk_sam9x5_main()
A Dcompat.c757 u32 num_parents; member
802 for (i = 0; i < priv->num_parents; i++) { in generic_clk_set_rate()
865 u32 num_parents; in generic_clk_of_to_plat() local
867 num_parents = fdtdec_get_int_array_count(gd->fdt_blob, in generic_clk_of_to_plat()
871 if (!num_parents) in generic_clk_of_to_plat()
874 priv->num_parents = num_parents; in generic_clk_of_to_plat()
/u-boot/drivers/clk/imx/
A Dclk.h116 int num_parents, void (*fixup)(u32 *val));
120 const char * const *parents, int num_parents, in imx_clk_mux_flags() argument
123 return clk_register_mux(NULL, name, parents, num_parents, in imx_clk_mux_flags()
131 int num_parents, unsigned long flags) in imx_clk_mux2_flags() argument
133 return clk_register_mux(NULL, name, parents, num_parents, in imx_clk_mux2_flags()
140 int num_parents) in imx_clk_mux() argument
142 return clk_register_mux(NULL, name, parents, num_parents, in imx_clk_mux()
150 const char * const *parents, int num_parents) in imx_clk_busy_mux() argument
152 return clk_register_mux(NULL, name, parents, num_parents, in imx_clk_busy_mux()
159 int num_parents) in imx_clk_mux2() argument
[all …]
A Dclk-composite-8m.c122 int num_parents, void __iomem *reg, in imx8m_clk_composite_flags() argument
137 mux->num_parents = num_parents; in imx8m_clk_composite_flags()
159 parent_names, num_parents, in imx8m_clk_composite_flags()
/u-boot/drivers/pwm/
A Dpwm-meson.c88 unsigned int num_parents; member
290 if (p >= data->num_parents) { in meson_pwm_probe()
368 for (p = 0 ; p < data->num_parents ; ++p) { in meson_pwm_probe()
379 if (p == data->num_parents) { in meson_pwm_probe()
418 .num_parents = ARRAY_SIZE(pwm_gxbb_parent_ids),
431 .num_parents = ARRAY_SIZE(pwm_gxbb_ao_parent_ids),
446 .num_parents = ARRAY_SIZE(pwm_axg_ee_parent_ids),
455 .num_parents = ARRAY_SIZE(pwm_axg_ao_parent_ids),
471 .num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_ids),
480 .num_parents = ARRAY_SIZE(pwm_g12a_ao_cd_parent_ids),
[all …]
/u-boot/drivers/clk/mediatek/
A Dclk-mtk.h118 signed char num_parents; member
131 .num_parents = ARRAY_SIZE(_parents), \
145 .num_parents = ARRAY_SIZE(_parents), \
163 .num_parents = ARRAY_SIZE(_parents), \
/u-boot/drivers/clk/ti/
A Dclk-sci.c125 u8 num_parents; in ti_sci_clk_set_parent() local
136 ret = cops->get_num_parents(sci, clk->id, clk->data, &num_parents); in ti_sci_clk_set_parent()
142 if (num_parents < 2) { in ti_sci_clk_set_parent()
150 if (parent_cid >= num_parents) { in ti_sci_clk_set_parent()
/u-boot/include/
A Dsandbox-clk.h79 int num_parents) in sandbox_clk_mux() argument
81 return clk_register_mux(NULL, name, parents, num_parents, in sandbox_clk_mux()
/u-boot/include/linux/
A Dclk-provider.h67 u8 num_parents; member
221 const char * const *parent_names, int num_parents,
240 const char * const *parent_names, u8 num_parents,
/u-boot/drivers/clk/kendryte/
A Dclk.c247 u8 num_parents; member
257 .num_parents = ARRAY_SIZE(parents), \
367 mux->num_parents = params->num_parents; in k210_create_mux()
424 int num_parents; in k210_register_comp() local
438 num_parents = 1; in k210_register_comp()
446 num_parents = mux->num_parents; in k210_register_comp()
461 comp = clk_register_composite(NULL, name, parent_names, num_parents, in k210_register_comp()
/u-boot/drivers/clk/uniphier/
A Dclk-uniphier-mio.c34 .num_parents = 8, \
A Dclk-uniphier.h34 u8 num_parents; member
A Dclk-uniphier-core.c47 for (i = 0; i < mux->num_parents; i++) { in uniphier_clk_mux_set_parent()
69 for (i = 0; i < mux->num_parents; i++) in uniphier_clk_mux_get_parent()
203 for (i = 0; i < data->data.mux.num_parents; i++) { in __uniphier_clk_set_rate()
/u-boot/arch/arm/include/asm/arch-tegra/
A Dbpmp_abi.h889 uint8_t num_parents; member

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