| /u-boot/drivers/rng/ |
| A D | Kconfig | 5 Enable driver model for random number generator(rng) devices.
16 Enable support for hardware random number generator
20 bool "Sandbox random number generator"
24 Enable random number generator for sandbox. This is an
35 bool "Enable random number generator for STM32MP1"
42 bool "Enable random number generator for rockchip crypto rng"
46 Enable random number generator for rockchip.This driver is
50 bool "Broadcom iProc RNG200 random number generator"
54 Enable random number generator for RPI4.
|
| /u-boot/doc/usage/ |
| A D | partitions.rst | 26 The device number. This defaults to 0.
29 The hardware partition number. All devices have at least one hardware
34 user-created partitions. The default hardware partition number is 0.
37 The partition number, starting from 1. The partition number 0 specifies
52 The device number as an offset from ``a``. For example, device
53 number 2 would have a device letter of ``c``.
56 The partition number. This is the same as above.
68 and partition number 3::
78 0, and partition number 0::
|
| A D | load.rst | 18 The number of transferred bytes is saved in the environment variable filesize.
25 device number
28 partition number, defaults to 0 (whole device)
38 maximum number of bytes to load
41 number of bytes to skip
72 even if the number of bytes is less then the specified length.
|
| /u-boot/doc/api/ |
| A D | rng.rst | 4 Random number generation
7 Hardware random number generation
13 Pseudo random number generation
|
| /u-boot/arch/arm/cpu/armv7/ |
| A D | cache_v7_asm.S | 45 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
48 ands r7, r7, r1, lsr #13 @ extract max number of the index size
54 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
55 ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
57 THUMB( orr r11, r11, r6 ) @ factor index number into r11
64 add r10, r10, #2 @ increment cache number
115 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
118 ands r7, r7, r1, lsr #13 @ extract max number of the index size
125 ARM( orr r11, r11, r9, lsl r2 ) @ factor index number into r11
127 THUMB( orr r11, r11, r6 ) @ factor index number into r11
[all …]
|
| /u-boot/doc/device-tree-bindings/ |
| A D | root.txt | 4 - serial-number : a string representing the device's serial number
|
| /u-boot/doc/device-tree-bindings/gpio/ |
| A D | intel,apl-gpio.txt | 11 [pin number within the gpio controller]
15 - Pin number: is a GPIO pin number between 0 and 244
|
| A D | mscc_sgpio.txt | 3 The MSCC serial GPIO extends the number or GPIO's on the system by
5 strobe pin. By attaching a number of (external) shift registers, the
14 - #gpio-cells : Should be two. The first cell is the pin number and the
|
| A D | nvidia,tegra186-gpio.txt | 32 a number of GPIOs. Thus, each GPIO is named according to an alphabetical port
36 The number of ports implemented by each GPIO controller varies. The number of
48 Each GPIO controller can generate a number of interrupt signals. Each signal
50 number of interrupt signals generated by a controller varies as a rough function
51 of the number of ports it implements. Note that the HW documentation refers to
90 order the HW manual describes them. The number of entries required varies
102 - The first cell is the pin number.
116 - The first cell is the GPIO number.
|
| A D | gpio-samsung.txt | 12 [pin number within the gpio controller]
18 - Pin number: is a value between 0 to 7.
|
| /u-boot/doc/device-tree-bindings/pci_endpoint/ |
| A D | cdns,cdns-pcie-ep.txt | 8 - max-functions: Maximum number of functions that can be configured (default 1).
9 - cdns,max-outbound-regions: Set to maximum number of outbound regions (default 8)
|
| /u-boot/board/warp7/ |
| A D | Kconfig | 10 int "Partition number to use for root filesystem"
13 The partition number to use for root filesystem this is the
|
| /u-boot/doc/device-tree-bindings/pinctrl/ |
| A D | bcm6838-pinctrl.txt | 6 - brcm,pins-count: the number of pin
7 - brcm,functions-count: the number of function
|
| /u-boot/doc/device-tree-bindings/exynos/ |
| A D | isp-spi.txt | 6 which will have a value beyond the maximum number of interrupts exynos5 can
12 - interrupts : A value which is beyond the maximum number of interrupts
|
| /u-boot/doc/device-tree-bindings/memory-controllers/ |
| A D | st,stm32-fmc.txt | 10 number of columns
11 number of rows
13 number of intenal banks in memory
|
| /u-boot/doc/ |
| A D | README.ubi | 62 UBI: number of good PEBs: 8
63 UBI: number of bad PEBs: 0
66 UBI: number of internal volumes: 1
67 UBI: number of user volumes: 1
69 UBI: total number of reserved PEBs: 8
70 UBI: number of PEBs reserved for bad PEB handling: 0
126 UBI: number of good PEBs: 8
127 UBI: number of bad PEBs: 0
133 UBI: number of internal volumes: 1
134 UBI: number of user volumes: 1
[all …]
|
| /u-boot/doc/device-tree-bindings/misc/ |
| A D | intel,irq-router.txt | 24 The second cell is the total number of PIRQ links the router supports.
27 number (0 for PIRQA, 1 for PIRQB, etc). The second cell is the PIRQ routing
35 bus number, device number and function number encoding with PCI_BDF() macro.
|
| /u-boot/doc/device-tree-bindings/interrupt-controller/ |
| A D | intel,acpi-gpe.txt | 10 - #interrupt-cells : The number of cells to define the interrupts. Must be 2:
11 cell 0: interrupt number (normally >=32 since GPEs below that are reserved)
|
| /u-boot/doc/device-tree-bindings/spi/ |
| A D | spi-bus.txt | 10 - #address-cells - number of cells required to define a chip select
26 - num-cs : total number of chipselects
28 If cs-gpios is used the number of chip select will automatically increased
58 - spi-tx-bus-width - (optional) The bus width(number of data wires) that
60 - spi-rx-bus-width - (optional) The bus width(number of data wires) that
71 If a gpio chipselect is used for the SPI slave the gpio number will be passed
|
| A D | spi-zynq.txt | 8 number.
17 If a decoder is used, this will be the number of
|
| /u-boot/drivers/usb/dwc3/ |
| A D | gadget.h | 98 static inline u32 dwc3_gadget_ep_get_transfer_index(struct dwc3 *dwc, u8 number) in dwc3_gadget_ep_get_transfer_index() argument
102 res_id = dwc3_readl(dwc->regs, DWC3_DEPCMD(number)); in dwc3_gadget_ep_get_transfer_index()
|
| /u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| A D | README.pci_iommu_extra | 14 - for a SRIOV capable PCI EP identified by its B.D.F specify the maximum number
31 - "vfs=<number>" to specify that for the PCI EP identified previously by
32 the <bdf> to include mappings for <number> of VFs.
33 The variant "noari_vfs=<number>" is available to disable taking ARI into
|
| /u-boot/arch/mips/dts/ |
| A D | mrvl,cn73xx.dtsi | 26 * 1) Source number (20 significant bits)
37 /* The chip select number and offset */
56 * 1) GPIO pin number (0..15)
164 * 2) GPIO pin number
196 * 2) GPIO pin number
|
| /u-boot/arch/arm/cpu/armv7/ls102xa/ |
| A D | Kconfig | 34 int "Maximum number of CPUs permitted for LS102xA"
37 Set this number to the maximum number of possible CPUs in the SoC.
|
| /u-boot/drivers/pinctrl/uniphier/ |
| A D | pinctrl-uniphier.h | 63 unsigned number; member
112 .number = a, \
|