Searched refs:odt (Results 1 – 19 of 19) sorted by relevance
| /u-boot/doc/device-tree-bindings/clock/ |
| A D | rockchip,rk3288-dmc.txt | 21 …rockchip,odt-disable-freq: if ddr clock frequency low than odt-disable-freq,this driver should dis…
110 odt - 1 to enable DDR ODT, 0 to disable
135 rockchip,odt-disable-freq = <333000000>;
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| /u-boot/doc/device-tree-bindings/fsp/fsp2/apollolake/ |
| A D | fsp-m.txt | 157 - fspm,chX-odt-config: Channel Odt Config (X = 0-3)
161 - fspm,chX-odt-levels: Channel Odt Levels (X = 0-3)
263 fspm,ch0-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
269 fspm,ch1-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
275 fspm,ch2-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
281 fspm,ch3-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
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| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | sdram_rk3288.h | 99 u32 odt; member
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| A D | sdram_common.h | 45 unsigned int odt; member
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| A D | sdram_rk322x.h | 270 u32 odt; member
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| /u-boot/drivers/ram/rockchip/ |
| A D | sdram-px30-ddr3-detect-333.inc | 31 .odt = 0,
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| A D | sdram-px30-lpddr2-detect-333.inc | 31 .odt = 0,
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| A D | sdram-px30-lpddr3-detect-333.inc | 31 .odt = 0,
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| A D | sdram-px30-ddr4-detect-333.inc | 31 .odt = 0,
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| A D | sdram_rk3288.c | 268 sdram_params->base.odt); in pctl_cfg()
350 if (sdram_params->base.odt) { in phy_cfg()
882 sdram_params->base.odt ? 3 : 0); in sdram_init()
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| A D | sdram_rk3188.c | 291 if (sdram_params->base.odt) { in phy_cfg()
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| A D | sdram_rk3399.c | 374 if (params->base.odt == 1) { in phy_io_config()
658 if (params->base.odt == 1) { in set_ds_odt()
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| A D | sdram-rk3399-lpddr4-400.inc | 81 .odt = 1,
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| A D | sdram-rk3399-lpddr4-800.inc | 81 .odt = 1,
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| /u-boot/board/tbs/tbs2910/ |
| A D | tbs2910.cfg | 35 * use default 40 Ohm pad drive strength, no odt
91 /* read odt settings, 120 Ohm */
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| /u-boot/arch/x86/dts/ |
| A D | galileo.dts | 62 rd-odt-value = <DRAM_RD_ODT_OFF>;
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| A D | chromebook_coral.dts | 697 fspm,ch0-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
703 fspm,ch1-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
709 fspm,ch2-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
715 fspm,ch3-odt-config = <CHX_ODT_CONFIG_DDR4_CA_ODT>;
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| /u-boot/arch/arm/mach-sunxi/ |
| A D | Kconfig | 503 bool "sunxi dram odt enable"
511 Select this to enable dram odt (on die termination).
583 int "sunxi dram odt correction value"
586 Set the dram odt correction value (range -255 - 255). In allwinner
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| /u-boot/arch/arm/dts/ |
| A D | rk3288-veyron.dtsi | 225 rockchip,odt-disable-freq = <333000000>;
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