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Searched refs:operation (Results 1 – 25 of 93) sorted by relevance

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/u-boot/arch/arm/mach-uniphier/arm32/
A Dcache-uniphier.c95 u32 operation) in uniphier_cache_maint_common() argument
102 writel(UNIPHIER_SSCOQM_CE | operation, UNIPHIER_SSCOQM); in uniphier_cache_maint_common()
105 if (likely(UNIPHIER_SSCOQAD_IS_NEEDED(operation))) { in uniphier_cache_maint_common()
111 if (unlikely(UNIPHIER_SSCOQWM_IS_NEEDED(operation))) in uniphier_cache_maint_common()
121 static void uniphier_cache_maint_all(u32 operation) in uniphier_cache_maint_all() argument
123 uniphier_cache_maint_common(0, 0, 0, UNIPHIER_SSCOQM_S_ALL | operation); in uniphier_cache_maint_all()
129 u32 operation) in uniphier_cache_maint_range() argument
143 uniphier_cache_maint_all(operation); in uniphier_cache_maint_range()
157 UNIPHIER_SSCOQM_S_RANGE | operation); in uniphier_cache_maint_range()
/u-boot/include/xen/interface/io/
A Dblkif.h631 u8 operation; /* BLKIF_OP_??? */ member
644 u8 operation; /* BLKIF_OP_DISCARD */ member
654 u8 operation; /* BLKIF_OP_INDIRECT */ member
668 u8 operation; /* copied from request */ member
/u-boot/lib/efi_loader/
A Defi_gop.c90 u32 operation, efi_uintn_t sx, in gop_blt_int() argument
114 switch (operation) { in gop_blt_int()
132 switch (operation) { in gop_blt_int()
147 switch (operation) { in gop_blt_int()
162 switch (operation) { in gop_blt_int()
182 switch (operation) { in gop_blt_int()
201 switch (operation) { in gop_blt_int()
372 u32 operation, efi_uintn_t sx, in gop_blt() argument
386 switch (operation) { in gop_blt()
394 ret = gop_blt_buf_to_vid32(this, buffer, operation, sx, in gop_blt()
[all …]
/u-boot/doc/device-tree-bindings/misc/
A Dcros-ec.txt4 The device tree node which describes the operation of the CROS_EC interface
12 operation
14 operation
A Dintel-lpc.txt4 The device tree node which describes the operation of the Intel Low Pin
/u-boot/doc/
A DREADME.fuse7 (i.e. blown, set to 1) only once. The programming operation is irreversible. A
34 fuse words. This operation does not update the shadow cache.
41 Program fuse words. This operation directly affects the fusebox and is
49 hardware programming operation on these fuse bits).
55 The fusebox is unaffected, so following this operation, the shadow cache
A DREADME.fsl_iim37 this operation, the shadow registers are reloaded by the hardware (not
A DREADME.mxc_ocotp41 Following this operation, the shadow registers are not reloaded by the
/u-boot/drivers/mtd/nand/raw/
A Dmxc_nand_spl.c123 writenfc(NFC_CMD, &nfc->operation); in nfc_nand_command()
130 writenfc(NFC_ADDR, &nfc->operation); in nfc_nand_address()
171 writenfc(NFC_OUTPUT, &nfc->operation); in nfc_nand_data_output()
180 writenfc(NFC_OUTPUT, &nfc->operation); in nfc_nand_data_output()
A Dmxc_nand.h199 #define operation config2 macro
203 #define operation launch macro
/u-boot/drivers/usb/dwc3/
A DKconfig31 This wrapper supports Host and Peripheral operation modes.
39 This wrapper supports Host and Peripheral operation modes.
47 This wrapper supports Host and Peripheral operation modes.
/u-boot/board/freescale/ls1028a/
A DREADME33 - Up to 1.3 GHz operation
112 - Up to 1.3 GHz operation
129 - Lane 0: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 10
131 - Lane 1: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
133 - Lane 2: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
135 - Lane 3: supports PCIe Gen1/2/3 with x1, x2, and x4 operation, 1 Gbit
/u-boot/doc/device-tree-bindings/i2c/
A Dtegra20-i2c.txt9 - the pll_p_out3 clock, which can be used for fast operation. This
A Di2c-stm32.txt9 operation for I2C transfer
/u-boot/doc/device-tree-bindings/ata/
A Dintel-sata.txt4 The device tree node which describes the operation of the Intel Pantherpoint
/u-boot/arch/mips/cpu/
A Dstart.S40 li t9, 15 # UHI exception operation
42 sdbbp 1 # Invoke UHI operation
/u-boot/board/ti/omap5_uevm/
A DREADME12 Alternative Boot operation mode or Boot Sequence Option 1/2. In this
/u-boot/arch/arm/mach-stm32mp/cmd_stm32prog/
A Dstm32prog_serial.c634 u8 operation; in download_command() local
655 operation = (u8)((u32)address >> 24); in download_command()
658 switch (operation) { in download_command()
753 if (operation == PHASE_OTP) { in download_command()
762 if (operation == PHASE_PMIC) { in download_command()
/u-boot/board/ti/dra7xx/
A DREADME12 Alternative Boot operation mode or Boot Sequence Option 1/2. In this
/u-boot/doc/device-tree-bindings/reset/
A Dsyscon-reset.txt8 To assert a reset on some device, the equivalent of the following operation is
/u-boot/drivers/xen/
A Dpvblock.c383 switch (rsp->operation) { in blkfront_aio_poll()
391 rsp->operation == BLKIF_OP_READ ? in blkfront_aio_poll()
414 rsp->operation, status); in blkfront_aio_poll()
488 req->operation = write ? BLKIF_OP_WRITE : BLKIF_OP_READ; in blkfront_aio()
555 req->operation = op; in blkfront_push_operation()
/u-boot/doc/device-tree-bindings/spi/
A Dspi-stm32-qspi.txt10 - A pinctrl must be defined to set pins in mode of operation for QSPI transfer
/u-boot/drivers/ddr/marvell/a38x/
A Dddr3_training_ip_engine.h48 enum hws_training_load_op operation,
/u-boot/doc/device-tree-bindings/clock/
A Drockchip,rk3368-dmc.txt7 (a) a target-frequency (i.e. operating point) for the memory operation
/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
A DREADME.soc40 - Three PCIe 2.0 controllers, one supporting x4 operation
139 16-/8-bit operation (no ECC support)
146 Support for up to 6 GBaud operation
148 - One PCI Express Gen2 controller, supporting x1 operation
191 - Support for 10G operation
199 - Three PCIe 3.0 controllers, one supporting x4 operation
365 - Two PCIe 3.0 controllers, one supporting x4 operation

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