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Searched refs:outb (Results 1 – 25 of 47) sorted by relevance

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/u-boot/arch/x86/lib/
A Di8259.c28 outb(0xff, MASTER_PIC + IMR); in i8259_init()
29 outb(0xff, SLAVE_PIC + IMR); in i8259_init()
36 outb(0x20, MASTER_PIC + ICW2); in i8259_init()
37 outb(IR2, MASTER_PIC + ICW3); in i8259_init()
38 outb(ICW4_PM, MASTER_PIC + ICW4); in i8259_init()
48 outb(0x28, SLAVE_PIC + ICW2); in i8259_init()
49 outb(0x02, SLAVE_PIC + ICW3); in i8259_init()
50 outb(ICW4_PM, SLAVE_PIC + ICW4); in i8259_init()
53 outb(OCW2_SEOI | i, SLAVE_PIC + OCW2); in i8259_init()
127 outb((u8)(int_bits & 0xff), ELCR1); in configure_irq_trigger()
[all …]
A Di8254.c22 outb(countdown & 0xff, PIT_BASE + PIT_T2); in i8254_set_beep_freq()
23 outb((countdown >> 8) & 0xff, PIT_BASE + PIT_T2); in i8254_set_beep_freq()
33 outb(PIT_CMD_CTR1 | PIT_CMD_LOW | PIT_CMD_MODE2, in i8254_init()
35 outb(TIMER1_VALUE, PIT_BASE + PIT_T1); in i8254_init()
42 outb(PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3, in i8254_init()
55 outb(PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3, in i8254_enable_beep()
A Dearly_cmos.c19 outb(addr, CMOS_IO_PORT); in cmos_read8()
/u-boot/drivers/misc/
A Dnuvoton_nct6102d.c13 outb(reg, NCT_EFER); in superio_outb()
14 outb(val, NCT_EFDR); in superio_outb()
19 outb(reg, NCT_EFER); in superio_inb()
25 outb(NCT_ENTRY_KEY, NCT_EFER); /* Enter extended function mode */ in superio_enter()
26 outb(NCT_ENTRY_KEY, NCT_EFER); /* Again according to manual */ in superio_enter()
38 outb(NCT_EXIT_KEY, NCT_EFER); /* Leave extended function mode */ in superio_exit()
A Dsmsc_sio1007.c13 outb(reg, port); in sio1007_read()
20 outb(reg, port); in sio1007_write()
21 outb(val, port + 1); in sio1007_write()
35 outb(0x55, port); in sio1007_enable_serial()
49 outb(0xaa, port); in sio1007_enable_serial()
55 outb(0x55, port); in sio1007_enable_runtime()
64 outb(0xaa, port); in sio1007_enable_runtime()
79 outb(0x55, port); in sio1007_gpio_config()
87 outb(0xaa, port); in sio1007_gpio_config()
124 outb(data, port + reg); in sio1007_gpio_set_value()
A Dali512x.c44 outb(index, ALI_INDEX); in ali_write()
45 outb(value, ALI_DATA); in ali_write()
51 outb(index, ALI_INDEX);
57 outb(0x51, ALI_INDEX); \
58 outb(0x23, ALI_INDEX)
62 outb(0xbb, ALI_INDEX)
376 outb(reg, ALI_CIO_INDEX); /* select I/O register */ in ali512x_cio_out()
383 outb(data, ALI_CIO_DATA); in ali512x_cio_out()
397 outb(reg, ALI_CIO_INDEX); /* select I/O register */ in ali512x_cio_in()
A Dwinbond_w83627.c18 outb(WINBOND_ENTRY_KEY, port); in pnp_enter_conf_state()
19 outb(WINBOND_ENTRY_KEY, port); in pnp_enter_conf_state()
27 outb(WINBOND_EXIT_KEY, port); in pnp_exit_conf_state()
A Dsmsc_lpc47m.c14 outb(0x55, port); in pnp_enter_conf_state()
21 outb(0xaa, port); in pnp_exit_conf_state()
A Dcros_ec_lpc.c64 outb(*d, EC_LPC_ADDR_HOST_PACKET + i); in cros_ec_lpc_packet()
67 outb(EC_COMMAND_PROTOCOL_3, EC_LPC_ADDR_HOST_CMD); in cros_ec_lpc_packet()
118 outb(*d, args_addr + i); in cros_ec_lpc_command()
123 outb(*d, param_addr + i); in cros_ec_lpc_command()
127 outb(cmd, cmd_addr); in cros_ec_lpc_command()
/u-boot/drivers/i2c/
A Dintel_i2c.c113 outb(((dev & 0x7f) << 1) | 1, base + SMBXMITADD); in smbus_block_read()
115 outb(offset & 0xff, base + SMBHSTCMD); in smbus_block_read()
117 outb((inb(base + SMBHSTCTL) & (~(0x7) << 2)) | (0x5 << 2), in smbus_block_read()
120 outb(inb(base + SMBHSTSTAT), base + SMBHSTSTAT); in smbus_block_read()
173 outb(((dev & 0x7f) << 1) & ~0x01, base + SMBXMITADD); in smbus_block_write()
175 outb(offset, base + SMBHSTCMD); in smbus_block_write()
177 outb((inb(base + SMBHSTCTL) & (~(0x7) << 2)) | (0x5 << 2), in smbus_block_write()
180 outb(inb(base + SMBHSTSTAT), base + SMBHSTSTAT); in smbus_block_write()
183 outb(len, base + SMBHSTDAT0); in smbus_block_write()
187 outb(*buffer++, base + SMBBLKDAT); in smbus_block_write()
[all …]
/u-boot/arch/x86/cpu/qemu/
A Ddram.c18 outb(HIGH_RAM_ADDR, CMOS_ADDR_PORT); in qemu_get_low_memory_size()
20 outb(LOW_RAM_ADDR, CMOS_ADDR_PORT); in qemu_get_low_memory_size()
31 outb(HIGH_HIGHRAM_ADDR, CMOS_ADDR_PORT); in qemu_get_high_memory_size()
33 outb(MID_HIGHRAM_ADDR, CMOS_ADDR_PORT); in qemu_get_high_memory_size()
35 outb(LOW_HIGHRAM_ADDR, CMOS_ADDR_PORT); in qemu_get_high_memory_size()
/u-boot/board/imgtec/malta/
A Dsuperio.c52 outb(SIOCONF_ENTER_SETUP, SIO_CONF_PORT); in malta_superio_init()
56 outb(sio_config[i].key, SIO_CONF_PORT); in malta_superio_init()
57 outb(sio_config[i].data, SIO_DATA_PORT); in malta_superio_init()
61 outb(SIOCONF_EXIT_SETUP, SIO_CONF_PORT); in malta_superio_init()
/u-boot/arch/x86/include/asm/
A Dpnp_def.h38 outb(reg, port); in pnp_write_config()
39 outb(value, port + 1); in pnp_write_config()
46 outb(reg, port); in pnp_read_config()
A Dpost.h44 outb %al, $POST_PORT
50 outb(code, POST_PORT); in post_code()
/u-boot/drivers/net/
A Drtl8139.c252 outb(EE_ENB & ~EE_CS, ee_addr); in rtl8139_read_eeprom()
253 outb(EE_ENB, ee_addr); in rtl8139_read_eeprom()
259 outb(EE_ENB | dataval, ee_addr); in rtl8139_read_eeprom()
261 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); in rtl8139_read_eeprom()
265 outb(EE_ENB, ee_addr); in rtl8139_read_eeprom()
269 outb(EE_ENB | EE_SHIFT_CLK, ee_addr); in rtl8139_read_eeprom()
273 outb(EE_ENB, ee_addr); in rtl8139_read_eeprom()
278 outb(~EE_CS, ee_addr); in rtl8139_read_eeprom()
332 outb(RTL_REG_CHIPCMD_CMDRXENB | RTL_REG_CHIPCMD_CMDTXENB, in rtl8139_reset()
518 outb(0x00, priv->ioaddr + RTL_REG_CONFIG1); in rtl8139_init_common()
[all …]
/u-boot/arch/microblaze/include/asm/
A Dio.h49 #define outb(x, addr) ((void)writeb(x, addr)) macro
68 #define out_8(addr, x) outb(x, addr)
73 #define outb_p(val, port) outb((val), (port))
118 outb(*p++, port); in io_outsb()
/u-boot/drivers/timer/
A Dtsc_timer.c273 outb((inb(0x61) & ~0x02) | 0x01, 0x61); in quick_pit_calibrate()
284 outb(0xb0, 0x43); in quick_pit_calibrate()
287 outb(0xff, 0x42); in quick_pit_calibrate()
288 outb(0xff, 0x42); in quick_pit_calibrate()
/u-boot/drivers/sysreset/
A Dsysreset_x86.c93 outb(value, IO_PORT_RESET); in x86_sysreset_request()
120 outb(value, IO_PORT_RESET); in efi_reset_system()
/u-boot/arch/x86/cpu/coreboot/
A Dcoreboot.c74 outb(0xcb, 0xb2); in board_final_init()
/u-boot/test/dm/
A Dpci.c72 outb(2, io_addr); in dm_test_pci_swapcase()
93 outb(2, io_addr); in dm_test_pci_swapcase()
154 outb(2, io_addr); in dm_test_pci_mixed()
178 outb(2, io_addr); in dm_test_pci_mixed()
/u-boot/arch/xtensa/include/asm/
A Dio.h60 #define outb(val, port) writeb((val), (u8 *)((unsigned long)(port))) macro
67 #define outb_p(val, port) outb((val), (port))
/u-boot/arch/x86/lib/fsp1/
A Dfsp_common.c73 outb(SYS_RST | RST_CPU, IO_PORT_RESET); in arch_fsp_init()
/u-boot/arch/x86/cpu/intel_common/
A Dcpu.c115 outb(0x0, IO_PORT_RESET); in cpu_set_flex_ratio_to_tdp_nominal()
116 outb(SYS_RST | RST_CPU, IO_PORT_RESET); in cpu_set_flex_ratio_to_tdp_nominal()
/u-boot/arch/sh/include/asm/
A Dio.h84 #define outb(v, p) __raw_writeb(v, p) macro
100 #define outb_p(val, port) outb((val), (port))
115 #define out_8(port, val) outb(val, port)
/u-boot/arch/x86/cpu/
A Dpci.c45 outb(value, PCI_REG_DATA + (offset & 3)); in pci_x86_write_config()

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