Searched refs:pctl_base (Results 1 – 4 of 4) sorted by relevance
| /u-boot/drivers/ram/rockchip/ |
| A D | sdram_pctl_px30.c | 40 pctl_base + DDR_PCTL2_MRCTRL0); in pctl_write_mr()
41 writel(arg, pctl_base + DDR_PCTL2_MRCTRL1); in pctl_write_mr()
44 pctl_base + DDR_PCTL2_MRCTRL0); in pctl_write_mr()
46 pctl_base + DDR_PCTL2_MRCTRL1); in pctl_write_mr()
83 dis_auto_zq = pctl_dis_zqcs_aref(pctl_base); in pctl_write_vrefdq()
94 pctl_rest_zqcs_aref(pctl_base, dis_auto_zq); in pctl_write_vrefdq()
104 writel(ret, pctl_base + DDR_PCTL2_RFSHCTL3); in upctl2_update_ref_reg()
114 if (!(readl(pctl_base + DDR_PCTL2_ZQCTL0) & in pctl_dis_zqcs_aref()
123 upctl2_update_ref_reg(pctl_base); in pctl_dis_zqcs_aref()
137 upctl2_update_ref_reg(pctl_base); in pctl_rest_zqcs_aref()
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| A D | sdram_px30.c | 251 void __iomem *pctl_base = dram->pctl; in set_ctl_address_map() local
267 writel(0x1f, pctl_base + DDR_PCTL2_ADDRMAP0); in set_ctl_address_map()
289 clrsetbits_le32(pctl_base + DDR_PCTL2_ADDRMAP6 + in set_ctl_address_map()
354 void __iomem *pctl_base = dram->pctl; in data_training() local
360 pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL); in data_training()
361 writel(0, pctl_base + DDR_PCTL2_PWRCTL); in data_training()
370 writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL); in data_training()
436 void __iomem *pctl_base = dram->pctl; in enable_low_power() local
472 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1); in enable_low_power()
474 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1); in enable_low_power()
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| A D | sdram_rk3328.c | 221 void __iomem *pctl_base = dram->pctl; in set_ctl_address_map() local
228 setbits_le32(pctl_base + DDR_PCTL2_PCCFG, 1 << 8); in set_ctl_address_map()
236 void __iomem *pctl_base = dram->pctl; in data_training() local
242 pwrctl = readl(pctl_base + DDR_PCTL2_PWRCTL); in data_training()
243 writel(0, pctl_base + DDR_PCTL2_PWRCTL); in data_training()
252 writel(pwrctl, pctl_base + DDR_PCTL2_PWRCTL); in data_training()
323 void __iomem *pctl_base = dram->pctl; in enable_low_power() local
336 clrbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1); in enable_low_power()
338 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, 1); in enable_low_power()
339 setbits_le32(pctl_base + DDR_PCTL2_PWRCTL, (1 << 3)); in enable_low_power()
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| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| A D | sdram_pctl_px30.h | 128 void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num);
129 int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg,
131 int pctl_write_vrefdq(void __iomem *pctl_base, u32 rank, u32 vrefrate,
134 u32 pctl_dis_zqcs_aref(void __iomem *pctl_base);
135 void pctl_rest_zqcs_aref(void __iomem *pctl_base, u32 dis_auto_zq);
140 int pctl_cfg(void __iomem *pctl_base, struct ddr_pctl_regs *pctl_regs,
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