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Searched refs:per_pll_pllc0 (Results 1 – 4 of 4) sorted by relevance

/u-boot/arch/arm/mach-socfpga/include/mach/
A Dclock_manager_s10.h53 u32 per_pll_pllc0; member
/u-boot/drivers/clk/altera/
A Dclk-agilex.h43 u32 per_pll_pllc0; member
A Dclk-agilex.c287 CM_REG_WRITEL(plat, cfg->per_pll_pllc0, CLKMGR_PERPLL_PLLC0); in clk_basic_init()
/u-boot/arch/arm/mach-socfpga/
A Dclock_manager_s10.c99 writel(cfg->per_pll_pllc0, in cm_basic_init()

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