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Searched refs:per_pll_pllc1 (Results 1 – 4 of 4) sorted by relevance

/u-boot/arch/arm/mach-socfpga/include/mach/
A Dclock_manager_s10.h54 u32 per_pll_pllc1; member
/u-boot/drivers/clk/altera/
A Dclk-agilex.h44 u32 per_pll_pllc1; member
A Dclk-agilex.c288 CM_REG_WRITEL(plat, cfg->per_pll_pllc1, CLKMGR_PERPLL_PLLC1); in clk_basic_init()
/u-boot/arch/arm/mach-socfpga/
A Dclock_manager_s10.c101 writel(cfg->per_pll_pllc1, in cm_basic_init()

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