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Searched refs:period (Results 1 – 25 of 42) sorted by relevance

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/u-boot/drivers/video/exynos/
A Dexynos_pwm_bl.c27 pwm_config(pwm->pwm_id, 0, pwm->period); in exynos_pwm_backlight_update_status()
31 brightness * pwm->period / max, pwm->period); in exynos_pwm_backlight_update_status()
/u-boot/drivers/sound/
A Dsound.c15 const int period = freq ? sample_rate / freq : 0; in sound_create_square_wave() local
16 const int half = period / 2; in sound_create_square_wave()
32 for (i = 0; size && i < period - half; i++) { in sound_create_square_wave()
/u-boot/drivers/pwm/
A Drk_pwm.c62 unsigned long period, duty; in rk_pwm_set_config() local
77 period = lldiv((uint64_t)priv->freq * period_ns, in rk_pwm_set_config()
82 writel(period, priv->base + regs->period); in rk_pwm_set_config()
99 debug("%s: period=%lu, duty=%lu\n", __func__, period, duty); in rk_pwm_set_config()
164 .period = 0x08,
178 .period = 0x04,
193 .period = 0x04,
A Dsunxi_pwm.c81 u32 period = 0; in sunxi_pwm_set_config() local
86 period = lldiv(scaled_freq * period_ns, nsecs_per_sec); in sunxi_pwm_set_config()
87 if ((period - 1 <= SUNXI_PWM_CH0_PERIOD_MAX) && in sunxi_pwm_set_config()
88 best_period < period) { in sunxi_pwm_set_config()
89 best_period = period; in sunxi_pwm_set_config()
A DKconfig9 frequency/period can be controlled along with the proportion of that
17 supports a programmable period and duty cycle. A 32-bit counter is
31 programmable period and duty cycle for 2 independant channels.
38 programmable period and duty cycle.
45 programmable period and duty cycle. A 32-bit counter is used.
68 four channels with a programmable period and duty cycle. Only a
77 programmable period and duty cycle. A 16-bit counter is used.
A Dpwm-meson.c105 unsigned int duty, period, pre_div, cnt, duty_cnt; in meson_pwm_set_config() local
114 period = period_ns; in meson_pwm_set_config()
121 channel->polarity ? "true" : "false", duty, period); in meson_pwm_set_config()
131 pre_div = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * 0xffffLL); in meson_pwm_set_config()
137 cnt = div64_u64(fin_freq * (u64)period, NSEC_PER_SEC * (pre_div + 1)); in meson_pwm_set_config()
143 debug("%s%d: period=%u pre_div=%u cnt=%u\n", __func__, channeln, period, pre_div, cnt); in meson_pwm_set_config()
145 if (duty == period) { in meson_pwm_set_config()
/u-boot/board/freescale/m5253demo/
A Dm5253demo.c104 long period; in ide_set_reset() local
120 #define CALC_TIMING(t) (t + period - 1) / period in ide_set_reset()
121 period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */ in ide_set_reset()
/u-boot/doc/device-tree-bindings/pwm/
A Dpwm-sifive.txt4 supports one period for all channels in the PWM. All PWMs need to run at
5 the same period. The period also has significant restrictions on the values
6 it can achieve, which the driver rounds to the nearest achievable period.
A Dtegra20-pwm.txt10 cell is the period in nanoseconds.
A Dpwm.txt44 period in nanoseconds.
/u-boot/drivers/misc/
A Dstatus_led.c24 int period; member
98 if (++ld->cnt >= ld->period) { in status_led_tick()
100 ld->cnt -= ld->period; in status_led_tick()
/u-boot/board/freescale/m54455evb/
A Dm54455evb.c121 long period; in ide_set_reset() local
136 #define CALC_TIMING(t) (t + period - 1) / period in ide_set_reset()
137 period = 1000000000 / gd->bus_clk; /* period in ns */ in ide_set_reset()
/u-boot/arch/arm/mach-exynos/include/mach/
A Dpwm_backlight.h13 int period; member
/u-boot/arch/arm/include/asm/arch-rockchip/
A Dpwm.h12 unsigned long period; member
/u-boot/board/gateworks/gw_ventana/
A DKconfig25 gsc sleep - sleeps for a period of seconds
/u-boot/drivers/led/
A DKconfig51 period, without needing timers or extra code to handle the timing.
146 The LED blink period calculated from LED_STATUS_FREQ:
181 The LED blink period calculated from LED_STATUS_FREQ1:
216 The LED blink period calculated from LED_STATUS_FREQ2:
251 The LED blink period calculated from LED_STATUS_FREQ3:
286 The LED blink period calculated from LED_STATUS_FREQ4:
321 The LED blink period calculated from LED_STATUS_FREQ5:
/u-boot/board/freescale/common/
A Dqixis.c341 static char *period[9] = {"2s", "4s", "8s", "16s", "32s", in qixis_reset_cmd() local
349 for (i = 0; i < ARRAY_SIZE(period); i++) { in qixis_reset_cmd()
350 if (strcmp(argv[2], period[i]) == 0) { in qixis_reset_cmd()
/u-boot/doc/device-tree-bindings/i2c/
A Di2c-designware.txt32 This value which is by default 300ns is used to compute the tLOW period.
35 This value which is by default 300ns is used to compute the tHIGH period.
/u-boot/drivers/usb/gadget/
A Dpxa25x_udc.h109 ulong period; member
/u-boot/board/freescale/mx6memcal/
A DKconfig201 int "Refresh period"
205 Select the DDR refresh period.
218 This selects the number of refreshes (-1) during each period.
/u-boot/drivers/spi/
A Dmxc_spi.c35 u32 period; member
73 u32 period; member
490 reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ); in mxc_spi_claim_bus_internal()
/u-boot/doc/device-tree-bindings/clock/
A Drockchip,rk3288-dmc.txt25 …rockchip,auto-self-refresh-cnt: Self Refresh idle period. Memories are placed into Self-Refresh mo…
26 …rockchip,auto-power-down-cnt: Power-down idle period. Memories are placed into power-down mode if …
/u-boot/fs/fat/
A Dfat_write.c105 char *period; in set_name() local
120 period = strrchr(filename, '.'); in set_name()
123 pos = period + 1; in set_name()
124 period = 0; in set_name()
126 if (period) in set_name()
127 str2fat(dirent.ext, period + 1, sizeof(dirent.ext)); in set_name()
/u-boot/doc/
A DREADME.arm-caches52 in the short period after the cache was flushed but before the
/u-boot/arch/arm/dts/
A Dimx8mn-evk.dtsi47 linux,autosuspend-period = <125>;

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