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Searched refs:pgcr2 (Results 1 – 10 of 10) sorted by relevance

/u-boot/board/ti/ks2_evm/
A Dddr3_k2g.c34 .pgcr2 = 0x00F03D09ul,
74 .pgcr2 = 0x00F05159ul,
135 .pgcr2 = 0x00F03D09ul,
A Dddr3_cfg.c32 .pgcr2 = 0x00F07A12ul,
/u-boot/arch/arm/mach-keystone/include/mach/
A Dddr3.h32 unsigned int pgcr2; member
/u-boot/arch/arm/mach-sunxi/
A Ddram_sun8i_a33.c239 clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6)); in mctl_channel_init()
288 setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6); in mctl_channel_init()
A Ddram_sun8i_a83t.c322 clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6)); in mctl_channel_init()
380 setbits_le32(&mctl_ctl->pgcr2, 0x3 << 6); in mctl_channel_init()
/u-boot/arch/arm/include/asm/arch-sunxi/
A Ddram_sun8i_a33.h124 u32 pgcr2; /* 0x108 */ member
A Ddram_sun8i_a83t.h124 u32 pgcr2; /* 0x108 */ member
A Ddram_sun8i_a23.h198 u32 pgcr2; /* 0x8c */ member
/u-boot/arch/arm/mach-keystone/
A Dddr3_spd.c39 debug_ddr_cfg("pgcr2 0x%08X\n", ptr->pgcr2); in dump_phy_config()
360 spd_cb->phy_cfg.pgcr2 = (0xF << 20) | ((int)spd->t_refprd & 0x3ffff); in init_ddr3param()
A Dddr3.c59 __raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET); in ddr3_init_ddrphy()

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