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Searched refs:phase (Results 1 – 25 of 88) sorted by relevance

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/u-boot/arch/arm/mach-stm32mp/cmd_stm32prog/
A Dstm32prog_usb.c20 if (phase == data->phase) { in stm32prog_set_phase()
29 if (part->id == phase) { in stm32prog_set_phase()
31 data->phase = phase; in stm32prog_set_phase()
43 u8 phase; in stm32prog_cmd_write() local
57 phase = pt[0]; in stm32prog_cmd_write()
59 if (phase == PHASE_RESET) { in stm32prog_cmd_write()
79 int phase; in stm32prog_cmd_read() local
91 phase = stm32prog_data->phase; in stm32prog_cmd_read()
92 if (phase == PHASE_FLASHLAYOUT) in stm32prog_cmd_read()
97 *pt_buf++ = (u8)(phase & 0xFF); in stm32prog_cmd_read()
[all …]
A Dstm32prog_serial.c120 if (phase == PHASE_FLASHLAYOUT || phase > PHASE_LAST_USER) { in stm32prog_read()
136 if (part->id == phase) in stm32prog_read()
162 data->read_phase = phase; in stm32prog_read()
169 ret, phase, offset); in stm32prog_read()
361 data->phase = address; in stm32prog_start()
372 switch (data->phase) { in stm32prog_start()
516 int phase = data->phase; in get_phase_command() local
518 if (phase == PHASE_RESET || phase == PHASE_DO_RESET) { in get_phase_command()
537 if (phase == PHASE_RESET) in get_phase_command()
913 int phase = data->phase; in stm32prog_serial_loop() local
[all …]
A Dstm32prog.c1117 sprintf(devstr, "%d", phase); in stm32prog_alt_add_virt()
1128 int phase, i, alt_id; in dfu_init_entities() local
1148 for (phase = 1; in dfu_init_entities()
1151 phase++) { in dfu_init_entities()
1505 int phase, i; in stm32prog_next_phase() local
1509 phase = data->phase; in stm32prog_next_phase()
1510 switch (phase) { in stm32prog_next_phase()
1520 data->phase = PHASE_END; in stm32prog_next_phase()
1523 phase++; in stm32prog_next_phase()
1528 if (part->id == phase) { in stm32prog_next_phase()
[all …]
A Dstm32prog.h122 unsigned int phase; member
172 if (data->phase != PHASE_RESET) { \
174 data->phase = PHASE_RESET; \
/u-boot/drivers/ddr/marvell/axp/
A Dddr3_read_leveling.c339 u32 phase) in overrun() argument
413 phase = 0; in ddr3_read_leveling_single_cs_rl_mode()
519 if ((!ratio_2to1) && ((phase == 0) || (phase == 4))) in ddr3_read_leveling_single_cs_rl_mode()
561 phase++; in ddr3_read_leveling_single_cs_rl_mode()
573 phase++; in ddr3_read_leveling_single_cs_rl_mode()
590 phase++; in ddr3_read_leveling_single_cs_rl_mode()
765 phase = 0; in ddr3_read_leveling_single_cs_window_mode()
879 phase; in ddr3_read_leveling_single_cs_window_mode()
989 phase++; in ddr3_read_leveling_single_cs_window_mode()
1124 phase = 4; in ddr3_read_leveling_single_cs_window_mode()
[all …]
A Dddr3_write_leveling.c119 phase = in ddr3_write_leveling_hw()
345 phase = in ddr3_wl_supplement()
353 [P] = phase; in ddr3_wl_supplement()
366 phase = in ddr3_wl_supplement()
375 if ((phase == 0) in ddr3_wl_supplement()
382 phase = 0x0; in ddr3_wl_supplement()
386 [P] = phase; in ddr3_wl_supplement()
439 phase = in ddr3_wl_supplement()
542 phase = in ddr3_write_leveling_hw_reg_dimm()
1223 for (phase = 0; phase < phaseMax; phase++) { in ddr3_write_leveling_single_cs()
[all …]
A Dddr3_hw_training.c549 void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay) in ddr3_write_pup_reg() argument
559 reg |= (phase << REG_PHY_PHASE_OFFS) | delay; in ddr3_write_pup_reg()
1050 u32 pup, reg, phase; in ddr3_get_min_max_rl_phase() local
1057 phase = ((reg >> 8) & 0x7); in ddr3_get_min_max_rl_phase()
1059 if (phase < *min) in ddr3_get_min_max_rl_phase()
1060 *min = phase; in ddr3_get_min_max_rl_phase()
1062 if (phase > *max) in ddr3_get_min_max_rl_phase()
1063 *max = phase; in ddr3_get_min_max_rl_phase()
/u-boot/lib/efi_selftest/
A Defi_selftest_reset.c46 .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
54 .phase = EFI_SETUP_BEFORE_BOOTTIME_EXIT,
A Defi_selftest.c162 if (test->phase == EFI_SETUP_BEFORE_BOOTTIME_EXIT || in need_reset()
163 test->phase == EFI_SETUP_AFTER_BOOTTIME_EXIT) in need_reset()
212 void efi_st_do_tests(const u16 *testname, unsigned int phase, in efi_st_do_tests() argument
224 if (test->phase != phase) in efi_st_do_tests()
A Defi_selftest_unaligned.c64 .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
A Defi_selftest_watchdog.c217 .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
225 .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
A Defi_selftest_exitbootservices.c85 .phase = EFI_SETUP_BEFORE_BOOTTIME_EXIT,
A Defi_selftest_mem.c74 .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
A Defi_selftest_tcg2.c72 .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
A Defi_selftest_textinput.c93 .phase = EFI_EXECUTE_BEFORE_BOOTTIME_EXIT,
/u-boot/arch/x86/include/asm/fsp/
A Dfsp_support.h38 u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase);
155 u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase);
A Dfsp_api.h29 enum fsp_phase phase; member
/u-boot/drivers/core/
A Ddevres.c47 enum devres_phase phase; member
111 dr->phase = DEVRES_PHASE_PROBE; in devres_add()
113 dr->phase = DEVRES_PHASE_OFDATA; in devres_add()
115 dr->phase = DEVRES_PHASE_BIND; in devres_add()
201 if (probe_and_ofdata_only && dr->phase == DEVRES_PHASE_BIND) in release_nodes()
233 devres_phase_name[dr->phase]); in dump_resources()
/u-boot/drivers/usb/emul/
A Dsandbox_flash.c59 enum cmd_phase phase; member
293 priv->phase = priv->transfer_len ? PHASE_DATA : PHASE_STATUS; in handle_ufi_command()
306 dev->name, pipe, ep, len, priv->phase); in sandbox_flash_bulk()
309 switch (priv->phase) { in sandbox_flash_bulk()
332 switch (priv->phase) { in sandbox_flash_bulk()
344 priv->phase = PHASE_STATUS; in sandbox_flash_bulk()
349 priv->phase = PHASE_STATUS; in sandbox_flash_bulk()
357 priv->phase = PHASE_START; in sandbox_flash_bulk()
/u-boot/arch/x86/lib/fsp2/
A Dfsp_support.c110 u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase) in fsp_notify() argument
124 params.phase = phase; in fsp_notify()
/u-boot/drivers/ram/stm32mp1/
A Dstm32mp1_tuning.c56 u8 phase; /* DQS phase */ member
722 last_right_ok.phase = phase_idx; in bit_deskew()
734 last_right_ok.phase = phase_idx - 1; in bit_deskew()
961 right_bound.phase = 0; in eye_training()
964 left_bound.phase = 0; in eye_training()
1057 left_bound.phase = ++phase_idx; in eye_training()
1064 left_bound.phase = 0; in eye_training()
1122 right_bound.phase = --phase_idx; in eye_training()
1169 left_bound.phase) / 2; in eye_training()
1176 if (((right_bound.phase + left_bound.phase) % 2 == 1) && in eye_training()
[all …]
/u-boot/include/
A Dsym53c8xx.h525 #define WHEN(phase) (0x00030000 | (phase)) argument
526 #define IF(phase) (0x00020000 | (phase)) argument
A Defi_selftest.h151 const enum efi_test_phase phase; member
/u-boot/arch/x86/lib/fsp1/
A Dfsp_support.c169 u32 fsp_notify(struct fsp_header *fsp_hdr, u32 phase) in fsp_notify() argument
185 params.phase = phase; in fsp_notify()
/u-boot/drivers/nvme/
A Dnvme.c188 u16 phase = nvmeq->cq_phase; in nvme_submit_sync_cmd() local
200 if ((status & 0x01) == phase) in nvme_submit_sync_cmd()
210 status, phase, head); in nvme_submit_sync_cmd()
214 phase = !phase; in nvme_submit_sync_cmd()
218 nvmeq->cq_phase = phase; in nvme_submit_sync_cmd()
228 phase = !phase; in nvme_submit_sync_cmd()
232 nvmeq->cq_phase = phase; in nvme_submit_sync_cmd()

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