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Searched refs:phy_addr (Results 1 – 25 of 79) sorted by relevance

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/u-boot/drivers/net/phy/
A Dmv88e6352.c35 static int sw_wait_rdy(const char *devname, u8 phy_addr) in sw_wait_rdy() argument
65 ret = sw_wait_rdy(devname, phy_addr); in sw_reg_read()
76 ret = sw_wait_rdy(devname, phy_addr); in sw_reg_read()
80 ret = miiphy_read(devname, phy_addr, DATA_REG, data); in sw_reg_read()
91 ret = sw_wait_rdy(devname, phy_addr); in sw_reg_write()
107 ret = sw_wait_rdy(devname, phy_addr); in sw_reg_write()
180 ret = ppu_disable(devname, phy_addr); in mv88e_sw_program()
187 ret = sw_reg_write(devname, phy_addr, regs[i].port, in mv88e_sw_program()
191 ppu_enable(devname, phy_addr); in mv88e_sw_program()
197 ret = ppu_enable(devname, phy_addr); in mv88e_sw_program()
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A Dca_phy.c26 u8 phy_addr; in __internal_phy_init() local
30 for (phy_addr = 4; phy_addr > 0; phy_addr--) { in __internal_phy_init()
31 phydev->addr = phy_addr; in __internal_phy_init()
42 for (phy_addr = 1; phy_addr < 5; phy_addr++) { in __internal_phy_init()
44 phydev->addr = phy_addr; in __internal_phy_init()
54 __func__, phy_addr, data); in __internal_phy_init()
/u-boot/board/freescale/t104xrdb/
A Deth.c24 int phy_addr = 0; in board_eth_init() local
71 phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR; in board_eth_init()
73 phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR; in board_eth_init()
75 phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR; in board_eth_init()
76 fm_info_set_phy_address(i, phy_addr); in board_eth_init()
84 phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR; in board_eth_init()
86 phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR; in board_eth_init()
87 fm_info_set_phy_address(i, phy_addr); in board_eth_init()
115 phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i; in board_eth_init()
119 vsc9953_port_info_set_phy_address(i, phy_addr); in board_eth_init()
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/u-boot/drivers/net/ti/
A Ddavinci_emac.c63 #define emac_gigabit_enable(phy_addr) davinci_eth_gigabit_enable(phy_addr) argument
75 static int gen_init_phy(int phy_addr);
77 static int gen_get_link_speed(int phy_addr);
78 static int gen_auto_negotiate(int phy_addr);
220 ((phy_addr & 0x1f) << 16), in davinci_eth_phy_read()
245 ((phy_addr & 0x1f) << 16) | in davinci_eth_phy_write()
257 static int gen_init_phy(int phy_addr) in gen_init_phy() argument
261 if (gen_get_link_speed(phy_addr)) { in gen_init_phy()
263 ret = gen_get_link_speed(phy_addr); in gen_init_phy()
287 static int gen_get_link_speed(int phy_addr) in gen_get_link_speed() argument
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A Ddavinci_emac.h293 int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data);
294 int davinci_eth_phy_write(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t data);
298 int (*init)(int phy_addr);
299 int (*is_phy_connected)(int phy_addr);
300 int (*get_link_speed)(int phy_addr);
301 int (*auto_negotiate)(int phy_addr);
/u-boot/drivers/net/pfe_eth/
A Dpfe_mdio.c19 static int pfe_write_addr(struct mii_dev *bus, int phy_addr, int dev_addr, in pfe_write_addr() argument
29 phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT); in pfe_write_addr()
53 static int pfe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr, in pfe_phy_read() argument
67 pfe_write_addr(bus, phy_addr, dev_addr, reg_addr); in pfe_phy_read()
72 phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT); in pfe_phy_read()
103 phy_addr, reg_addr, val); in pfe_phy_read()
108 static int pfe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr, in pfe_phy_write() argument
121 pfe_write_addr(bus, phy_addr, dev_addr, reg_addr); in pfe_phy_write()
126 phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT); in pfe_phy_write()
152 debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phy_addr, in pfe_phy_write()
/u-boot/board/freescale/ls1088a/
A Deth_ls1088aqds.c102 int phy_addr = 0; in sgmii_configure_repeater() local
135 phy_addr = 4; in sgmii_configure_repeater()
139 phy_addr = 0; in sgmii_configure_repeater()
143 phy_addr = 0xc; in sgmii_configure_repeater()
147 phy_addr = 8; in sgmii_configure_repeater()
171 miiphy_write(dev, phy_addr, 0x1f, 0); in sgmii_configure_repeater()
228 miiphy_write(dev, phy_addr, 0x1f, 0); in sgmii_configure_repeater()
240 int phy_addr = 0; in qsgmii_configure_repeater() local
281 phy_addr = 8; in qsgmii_configure_repeater()
289 phy_addr = 0xc; in qsgmii_configure_repeater()
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/u-boot/drivers/phy/marvell/
A Dcomphy_a3700.c177 reg_set16(phy_addr(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0); in comphy_pcie_power_up()
182 reg_set16(phy_addr(PCIE, GLOB_CLK_SRC_LO), bf_cfg_sel_20b, 0); in comphy_pcie_power_up()
192 reg_set16(phy_addr(PCIE, PWR_MGM_TIM1), 0x10C, 0xFFFF); in comphy_pcie_power_up()
202 reg_set16(phy_addr(PCIE, MISC_REG0), in comphy_pcie_power_up()
216 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC63, 0xFFFF); in comphy_pcie_power_up()
219 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC62, 0xFFFF); in comphy_pcie_power_up()
232 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0); in comphy_pcie_power_up()
235 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0); in comphy_pcie_power_up()
240 reg_set16(phy_addr(PCIE, GLOB_PHY_CTRL0), in comphy_pcie_power_up()
248 ret = comphy_poll_reg(phy_addr(PCIE, LANE_STAT1), /* address */ in comphy_pcie_power_up()
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/u-boot/drivers/net/
A Dmcfmii.c144 return info->phy_addr; in mii_discover_phy()
247 info->phy_addr = mii_discover_phy(info); in __mii_init()
249 if (info->phy_addr == -1) in __mii_init()
256 miiphy_read(dev->name, info->phy_addr, MII_BMCR, &status); in __mii_init()
267 miiphy_read(dev->name, info->phy_addr, MII_BMSR, &status); in __mii_init()
277 info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; in __mii_init()
278 info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); in __mii_init()
A Ddnet.c33 unsigned short phy_addr; member
77 dnet->phy_addr, reg, value); in dnet_mdio_write()
90 tmp |= (dnet->phy_addr << 8); in dnet_mdio_write()
116 value = (dnet->phy_addr << 8); in dnet_mdio_read()
130 dnet->phy_addr, reg, value); in dnet_mdio_read()
253 dnet->phy_addr = i; in dnet_phy_init()
361 int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr) in dnet_eth_initialize() argument
377 dnet->phy_addr = phy_addr; in dnet_eth_initialize()
A Dmtk_eth.c180 int phy_addr; member
464 u8 phy_addr; in mt7531_mii_ind_read() local
478 u8 phy_addr; in mt7531_mii_ind_write() local
491 u8 phy_addr; in mt7531_mmd_ind_read() local
511 u8 phy_addr; in mt7531_mmd_ind_write() local
599 return priv->mmd_read(priv, phy_addr, 0x1f, reg); in mt753x_core_reg_read()
606 priv->mmd_write(priv, phy_addr, 0x1f, reg, val); in mt753x_core_reg_write()
671 u16 phy_addr, phy_val; in mt7530_setup() local
692 phy_val = priv->mii_read(priv, phy_addr, MII_BMCR); in mt7530_setup()
874 u16 phy_addr, phy_val; in mt7531_setup() local
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A Duli526x.c137 u8 phy_addr; member
379 db->phy_addr = 1; in uli526x_init()
385 db->phy_addr = phy_tmp; in uli526x_init()
403 db->phy_addr, 0, db->chip_id); in uli526x_init()
405 uli_phy_write(db->ioaddr, db->phy_addr, 0, in uli526x_init()
780 db->phy_addr, 4, db->chip_id) & ~0x01e0; in uli526x_set_phyxcer()
839 phy_write_1bit(ioaddr, phy_addr & i ? in uli_phy_write()
869 return phy_readby_cr10(iobase, phy_addr, offset); in uli_phy_read()
887 phy_write_1bit(ioaddr, phy_addr & i ? in uli_phy_read()
912 cr10_value = phy_addr; in phy_readby_cr10()
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A Dmt7620-eth.c233 int phy_addr; member
563 if (priv->port_cfg[0].phy_addr > 0) in mt7620_gsw_ephy_init()
566 if (priv->port_cfg[1].phy_addr > 0) in mt7620_gsw_ephy_init()
674 if (priv->port_cfg[0].phy_addr < 0 && priv->port_cfg[1].phy_addr < 0) in mt7620_gsw_setup_phy_polling()
677 if (priv->port_cfg[0].phy_addr > 0 && priv->port_cfg[1].phy_addr > 0) { in mt7620_gsw_setup_phy_polling()
678 phy_addr_st = priv->port_cfg[0].phy_addr; in mt7620_gsw_setup_phy_polling()
1053 u32 phy_addr; in mt7620_eth_parse_gsw_port() local
1118 if (phy_addr > 31 || (idx == 0 && phy_addr < 3) || in mt7620_eth_parse_gsw_port()
1119 (idx == 1 && phy_addr < 4)) { in mt7620_eth_parse_gsw_port()
1124 priv->port_cfg[idx].phy_addr = phy_addr; in mt7620_eth_parse_gsw_port()
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A Dftgmac100.c86 u32 phy_addr; member
102 static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr, in ftgmac100_mdio_read() argument
112 FTGMAC100_PHYCR_PHYAD(phy_addr) | in ftgmac100_mdio_read()
122 priv->phydev->dev->name, phy_addr, reg_addr); in ftgmac100_mdio_read()
131 static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr, in ftgmac100_mdio_write() argument
141 FTGMAC100_PHYCR_PHYAD(phy_addr) | in ftgmac100_mdio_write()
154 priv->phydev->dev->name, phy_addr, reg_addr); in ftgmac100_mdio_write()
223 phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode); in ftgmac100_phy_init()
582 priv->phy_addr = 0; in ftgmac100_probe()
585 priv->phy_addr = CONFIG_PHY_ADDR; in ftgmac100_probe()
A Dmacb.c134 unsigned short phy_addr; member
520 macb_mdio_write(macb, macb->phy_addr, MII_ADVERTISE, adv); in macb_phy_reset()
526 status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR); in macb_phy_reset()
546 printf("%s: PHY present at %d\n", name, macb->phy_addr); in macb_phy_find()
552 macb->phy_addr = i; in macb_phy_find()
696 macb->phydev = phy_connect(macb->bus, macb->phy_addr, dev, in macb_phy_init()
711 status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR); in macb_phy_init()
717 status = macb_mdio_read(macb, macb->phy_addr, MII_BMSR); in macb_phy_init()
738 lpa = macb_mdio_read(macb, macb->phy_addr, MII_STAT1000); in macb_phy_init()
773 lpa = macb_mdio_read(macb, macb->phy_addr, MII_LPA); in macb_phy_init()
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/u-boot/arch/mips/mach-octeon/
A Dcvmx-bootmem.c809 CAST_ULL(phy_addr), CAST_ULL(size)); in __cvmx_bootmem_phy_free()
815 if (!size || !phy_addr) in __cvmx_bootmem_phy_free()
828 else if (phy_addr + size == cur_addr) { in __cvmx_bootmem_phy_free()
830 cvmx_bootmem_phy_set_next(phy_addr, in __cvmx_bootmem_phy_free()
832 cvmx_bootmem_phy_set_size(phy_addr, in __cvmx_bootmem_phy_free()
848 while (cur_addr && phy_addr > cur_addr) { in __cvmx_bootmem_phy_free()
864 cvmx_bootmem_phy_set_next(phy_addr, 0); in __cvmx_bootmem_phy_free()
877 if (phy_addr + size == cur_addr) { in __cvmx_bootmem_phy_free()
887 } else if (phy_addr + size == cur_addr) { in __cvmx_bootmem_phy_free()
889 cvmx_bootmem_phy_set_size(phy_addr, in __cvmx_bootmem_phy_free()
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/u-boot/include/
A Dmv88e6352.h71 int mv88e_sw_reset(const char *devname, u8 phy_addr);
72 int mv88e_sw_program(const char *devname, u8 phy_addr,
A Dnetdev.h41 int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
57 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
62 int phy_addr);
/u-boot/drivers/net/ldpaa_eth/
A Dldpaa_wriop.c39 dpmac_info[dpmac_id].phy_addr[phy_num] = -1; in wriop_init_dpmac()
52 dpmac_info[dpmac_id].phy_addr[phy_num] = -1; in wriop_init_dpmac_enet_if()
138 dpmac_info[i].phy_addr[phy_num] = address; in wriop_set_phy_address()
152 return dpmac_info[i].phy_addr[phy_num]; in wriop_get_phy_address()
/u-boot/arch/arm/mach-rockchip/
A Dmake_fit_atf.py50 def append_bl31_node(file, atf_index, phy_addr, elf_entry): argument
52 data = 'bl31_0x%08x.bin' % phy_addr
60 file.write('\t\t\tload = <0x%08x>;\n' % phy_addr)
66 def append_tee_node(file, atf_index, phy_addr, elf_entry): argument
68 data = 'tee_0x%08x.bin' % phy_addr
76 file.write('\t\t\tload = <0x%08x>;\n' % phy_addr)
A Dsdram.c25 s64 phy_addr; member
31 s64 phy_addr; member
56 gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr in dram_init_banksize()
58 gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr + in dram_init_banksize()
/u-boot/drivers/net/octeontx/
A Dsmi.c263 int rxaui_phy_xs_init(struct mii_dev *bus, int phy_addr) in rxaui_phy_xs_init() argument
270 phy_id1 = octeontx_phy_read(bus, phy_addr, 1, 0x2); in rxaui_phy_xs_init()
271 phy_id2 = octeontx_phy_read(bus, phy_addr, 1, 0x3); in rxaui_phy_xs_init()
283 reg = octeontx_phy_read(bus, phy_addr, 4, 0x0); in rxaui_phy_xs_init()
287 octeontx_phy_write(bus, phy_addr, 4, 0x0, reg); in rxaui_phy_xs_init()
291 reg = octeontx_phy_read(bus, phy_addr, 4, 0x0); in rxaui_phy_xs_init()
301 octeontx_phy_write(bus, phy_addr, 4, 0xc003, 0x5); in rxaui_phy_xs_init()
/u-boot/drivers/net/mscc_eswitch/
A Dservalt_switch.c118 size_t phy_addr; member
404 size_t phy_addr, struct mii_dev *bus) in add_port_entry() argument
406 priv->ports[index].phy_addr = phy_addr; in add_port_entry()
419 size_t phy_addr; in servalt_probe() local
457 phy_addr = res.start; in servalt_probe()
477 add_port_entry(priv, i, phy_addr, bus); in servalt_probe()
486 phy_connect(priv->ports[i].bus, priv->ports[i].phy_addr, dev, in servalt_probe()
/u-boot/arch/arm/cpu/armv7/ls102xa/
A Dcpu.c104 static inline void set_pgtable(u32 *page_table, u32 index, u32 phy_addr) in set_pgtable() argument
106 u32 value = phy_addr | PMD_TYPE_TABLE; in set_pgtable()
113 static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr, in set_pgsection() argument
118 value = phy_addr | PMD_TYPE_SECT | PMD_SECT_AF; in set_pgsection()
/u-boot/board/freescale/mpc837xemds/
A Dmpc837xemds.c146 int phy_addr) in __ft_tsec_fixup() argument
181 phy_addr = cpu_to_fdt32(phy_addr); in __ft_tsec_fixup()
182 err = fdt_setprop(blob, off, "reg", &phy_addr, sizeof(phy_addr)); in __ft_tsec_fixup()

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