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Searched refs:phy_con1 (Results 1 – 6 of 6) sorted by relevance

/u-boot/arch/arm/mach-exynos/
A Ddmc_init_ddr3.c179 writel(val, &phy0_ctrl->phy_con1); in ddr3_mem_ctrl_init()
180 writel(val, &phy1_ctrl->phy_con1); in ddr3_mem_ctrl_init()
702 val = readl(&phy0_ctrl->phy_con1); in ddr3_mem_ctrl_init()
704 writel(val, &phy0_ctrl->phy_con1); in ddr3_mem_ctrl_init()
706 val = readl(&phy1_ctrl->phy_con1); in ddr3_mem_ctrl_init()
708 writel(val, &phy1_ctrl->phy_con1); in ddr3_mem_ctrl_init()
736 val = readl(&phy0_ctrl->phy_con1); in ddr3_mem_ctrl_init()
738 writel(val, &phy0_ctrl->phy_con1); in ddr3_mem_ctrl_init()
740 val = readl(&phy1_ctrl->phy_con1); in ddr3_mem_ctrl_init()
742 writel(val, &phy1_ctrl->phy_con1); in ddr3_mem_ctrl_init()
/u-boot/board/technexion/pico-imx7d/
A Dspl.c75 .phy_con1 = 0x10210100,
/u-boot/arch/arm/mach-exynos/include/mach/
A Ddmc.h331 unsigned int phy_con1; member
378 unsigned int phy_con1; member
/u-boot/arch/arm/mach-imx/mx7/
A Dddr.c96 writel(ddr_phy_regs_val->phy_con1, &ddr_phy_regs->phy_con1); in mx7_dram_cfg()
/u-boot/board/compulab/cl-som-imx7/
A Dspl.c69 .phy_con1 = 0x10210100,
/u-boot/arch/arm/include/asm/arch-mx7/
A Dmx7-ddr.h128 u32 phy_con1; /* 0x0004 */ member

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