| /u-boot/drivers/usb/host/ |
| A D | ehci-mx6.c | 153 void __iomem *phy_ctrl; in usb_phy_enable() local
161 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); in usb_phy_enable()
176 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); in usb_phy_enable()
180 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); in usb_phy_enable()
186 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | in usb_phy_enable()
195 void __iomem *phy_ctrl; in usb_phy_mode() local
199 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); in usb_phy_mode()
201 val = readl(phy_ctrl); in usb_phy_mode()
478 void *__iomem phy_ctrl, *__iomem phy_status; in ehci_usb_phy_mode() local
499 phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL); in ehci_usb_phy_mode()
[all …]
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| A D | ehci-vf.c | 90 void __iomem *phy_ctrl; in usb_phy_enable() local
94 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); in usb_phy_enable()
107 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); in usb_phy_enable()
111 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); in usb_phy_enable()
118 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | in usb_phy_enable()
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| /u-boot/arch/arm/mach-exynos/ |
| A D | dmc_init_ddr3.c | 281 *phy_ctrl) in dmc_get_read_offset_value()
283 return readl(&phy_ctrl->phy_con4); in dmc_get_read_offset_value()
293 setbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3); in ddr_phy_set_do_resync()
308 writel(offset, &phy_ctrl->phy_con4); in dmc_set_read_offset_value()
309 ddr_phy_set_do_resync(phy_ctrl); in dmc_set_read_offset_value()
360 dmc_set_read_offset_value(phy_ctrl, DEFAULT_DQS_X4); in test_shifts()
369 offsetr = dmc_get_read_offset_value(phy_ctrl); in test_shifts()
372 dmc_set_read_offset_value(phy_ctrl, offsetr); in test_shifts()
424 test_shifts(phy_ctrl, ch, left_limit, right_limit, left); in software_find_read_offset()
425 test_shifts(phy_ctrl, ch, right_limit, left_limit, right); in software_find_read_offset()
[all …]
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| /u-boot/drivers/ram/aspeed/ |
| A D | sdram_ast2500.c | 99 writel(0, ®s->phy_ctrl[0]); in ast2500_ddr_phy_init_process()
102 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); in ast2500_ddr_phy_init_process()
103 while ((readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT)) in ast2500_ddr_phy_init_process()
106 ®s->phy_ctrl[0]); in ast2500_ddr_phy_init_process()
111 writel(0, &info->regs->phy_ctrl[0]); in ast2500_sdrammc_set_vref()
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| A D | sdram_ast2600.c | 445 writel(SDRAM_PHYCTRL0_NRST, ®s->phy_ctrl[0]); in ast2600_sdramphy_kick_training()
447 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); in ast2600_sdramphy_kick_training()
451 data = readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT; in ast2600_sdramphy_kick_training()
474 writel(0, &info->regs->phy_ctrl[0]); in ast2600_sdramphy_init()
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| /u-boot/doc/device-tree-bindings/phy/ |
| A D | sun4i-usb-phy.txt | 18 * "phy_ctrl"
53 reg-names = "phy_ctrl", "pmu1", "pmu2";
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| /u-boot/arch/arm/include/asm/arch-aspeed/ |
| A D | sdram_ast2500.h | 120 u32 phy_ctrl[4]; member
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| A D | sdram_ast2600.h | 152 u32 phy_ctrl[4]; /* offset 0x60 ~ 0x6C */ member
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| /u-boot/drivers/net/ |
| A D | e1000.c | 2415 uint32_t phy_ctrl = 0; in e1000_set_d3_lplu_state() local
2437 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); in e1000_set_d3_lplu_state()
2507 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; in e1000_set_d3_lplu_state()
2550 uint32_t phy_ctrl = 0; in e1000_set_d0_lplu_state() local
2559 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); in e1000_set_d0_lplu_state()
2571 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; in e1000_set_d0_lplu_state()
2572 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state()
2574 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; in e1000_set_d0_lplu_state()
2619 phy_ctrl |= E1000_PHY_CTRL_D0A_LPLU; in e1000_set_d0_lplu_state()
2620 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); in e1000_set_d0_lplu_state()
[all …]
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| /u-boot/arch/arm/dts/ |
| A D | sun8i-a23.dtsi | 87 reg-names = "phy_ctrl", "pmu1";
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| A D | sun8i-a33.dtsi | 532 reg-names = "phy_ctrl", "pmu1";
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| A D | sun8i-v3s.dtsi | 290 reg-names = "phy_ctrl",
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| A D | am33xx.dtsi | 389 reg-names = "phy_ctrl", "wakeup";
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| A D | sun50i-h616.dtsi | 518 reg-names = "phy_ctrl",
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| A D | sun5i.dtsi | 331 reg-names = "phy_ctrl", "pmu1";
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| A D | sun8i-r40.dtsi | 249 reg-names = "phy_ctrl",
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| A D | sun50i-h6.dtsi | 659 reg-names = "phy_ctrl",
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| A D | sun8i-a83t.dtsi | 573 reg-names = "phy_ctrl",
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| A D | sunxi-h3-h5.dtsi | 263 reg-names = "phy_ctrl",
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| A D | sun4i-a10.dtsi | 460 reg-names = "phy_ctrl", "pmu1", "pmu2";
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| A D | sun50i-a64.dtsi | 571 reg-names = "phy_ctrl",
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| A D | sun6i-a31.dtsi | 485 reg-names = "phy_ctrl",
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| /u-boot/drivers/ram/ |
| A D | k3-am654-ddrss.c | 204 struct ddrss_ddrphy_ctrl_params *ctrl = &ddrss->params.phy_ctrl; in am654_ddrss_phy_configuration()
1004 (u32 *)&ddrss->params.phy_ctrl, in am654_ddrss_ofdata_to_priv()
1005 sizeof(ddrss->params.phy_ctrl) / sizeof(u32)); in am654_ddrss_ofdata_to_priv()
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| A D | k3-am654-ddrss.h | 1194 struct ddrss_ddrphy_ctrl_params phy_ctrl; member
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| /u-boot/arch/arm/mach-exynos/include/mach/ |
| A D | dp.h | 192 unsigned int phy_ctrl; member
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