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/u-boot/doc/usage/
A Daddrmap.rst16 The addrmap command is used to display non-identity virtual-physical memory
34 The second column indicates the physical address.
/u-boot/doc/
A DREADME.pcap6 The capture is stored on physical memory, and should be copied to
8 If networking works properly one can copy the capture file from physical memory
18 # Initialize pcap capture to physical address (0x100000) with maximum size of
A DREADME.mpc85xx-spin-table11 the physical address of this page, with WIMGE=0b01010. Core 0 also enables boot
15 core 0 puts the physical address of the spin table (which is in release.S and
21 the new space. The new TLB covers the physical address of the spin table page,
A DREADME.ubispl20 The maximum physical erase block size. Either a compile time
25 The maximum physical erase block count. Either a compile time
87 * MY_NAND_NR_SPL_PEBS is the number of physical erase blocks
/u-boot/doc/device-tree-bindings/clock/
A Drockchip,rk3368-dmc.txt9 (c) a memory-schedule (i.e. mapping from physical addresses to the address
45 controls the decoding of physical addresses to DRAM addressing (i.e. how
46 the physical address maps onto the address pins/chip-select of the device)
A Dmicrochip,pic32-clock.txt14 - reg: physical base address of the controller and length of memory mapped
A Dsnps,hsdk-cgu.txt9 - reg: the pair of physical base address and length of clock generation unit
/u-boot/arch/mips/mach-jz47xx/jz4780/
A DTODO4 - define the remaining register base addresses as physical addresses and establish a mapping with i…
/u-boot/doc/device-tree-bindings/gpio/
A Dnvidia,tegra186-gpio.txt15 register set. These registers exist in a single contiguous block of physical
25 controllers, these registers are exposed via multiple "physical aliases" in
28 just one of these physical aliases.
76 a) The single physical alias that this OS should use.
77 b) All physical aliases that exist in the controller. This is
79 the physical aliases.
84 Array of (physical base address, length) tuples.
/u-boot/doc/device-tree-bindings/serial/
A Dqca,ar9330-uart.txt7 - reg: Specifies the physical base address of the controller and
/u-boot/doc/device-tree-bindings/timer/
A Daltera_timer.txt6 - reg : Specifies base physical address and size of the registers.
/u-boot/board/freescale/ls1012ardb/
A DKconfig49 hex "PFE DDR physical base address"
105 hex "PFE DDR physical base address"
/u-boot/doc/device-tree-bindings/pwm/
A Dtegra20-pwm.txt7 - reg: physical base address and length of the controller's registers
/u-boot/doc/device-tree-bindings/i2c/
A Di2c-at91.txt7 - reg: physical base address of the controller and length of memory mapped
/u-boot/drivers/scsi/
A DKconfig7 hard drives and optical drives. The SCSI standards define physical
/u-boot/include/zfs/
A Dspa.h202 #define BP_SET_BIRTH(bp, logical, physical) \ argument
205 (bp)->blk_phys_birth = ((logical) == (physical) ? 0 : (physical)); \
/u-boot/drivers/
A DKconfig144 bool "Custom physical to bus address mapping"
146 Some SoCs use a different address map for CPU physical addresses and
/u-boot/doc/device-tree-bindings/phy/
A Dphy-mtk-tphy.txt4 T-phy controller supports physical layer functionality for a number of
12 - #address-cells: the number of cells used to represent physical
18 the child's base address to 0, the physical address
/u-boot/drivers/led/
A DKconfig129 to a physical LED is the responsibility of the __led_* function.
163 the value to a physical LED is the responsibility of the __led_*
198 the value to a physical LED is the responsibility of the __led_*
233 the value to a physical LED is the responsibility of the __led_*
268 the value to a physical LED is the responsibility of the __led_*
303 the value to a physical LED is the responsibility of the __led_*
/u-boot/board/keymile/
A DKconfig27 Start address of the physical RAM, which is the mounted /var folder.
36 Reserved physical RAM area at the end of memory for special purposes.
/u-boot/doc/device-tree-bindings/usb/
A Dmediatek,mtu3.txt9 - reg : specifies physical base address and size of the registers
30 - reg : specifies physical base address and size of the registers
/u-boot/doc/device-tree-bindings/video/
A Datmel-hlcdc.txt6 - reg: physical base address of the controller and length of memory mapped
/u-boot/board/freescale/ls1012aqds/
A DKconfig55 hex "PFE DDR physical base address"
/u-boot/board/freescale/ls1012afrdm/
A DKconfig37 hex "PFE DDR physical base address"
/u-boot/doc/mvebu/
A Darmada-8k-memory.txt4 The below desribes the physical memory layout for Marvell's Armada-8k SoC's.

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