/u-boot/drivers/ram/stm32mp1/ |
A D | stm32mp1_ddr.c | 215 DDRPHY_REG_DYN(pir), 573 void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir) in stm32mp1_ddrphy_init() argument 575 pir |= DDRPHYC_PIR_INIT; in stm32mp1_ddrphy_init() 576 writel(pir, &phy->pir); in stm32mp1_ddrphy_init() 578 (u32)&phy->pir, pir, readl(&phy->pir)); in stm32mp1_ddrphy_init() 677 u32 pir; in stm32mp1_ddr_init() local 792 pir = DDRPHYC_PIR_DLLSRST | DDRPHYC_PIR_DLLLOCK | DDRPHYC_PIR_ZCAL | in stm32mp1_ddr_init() 796 pir |= DDRPHYC_PIR_DRAMRST; /* only for DDR3 */ in stm32mp1_ddr_init() 798 stm32mp1_ddrphy_init(priv->phy, pir); in stm32mp1_ddr_init()
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A D | stm32mp1_ddr.h | 177 void stm32mp1_ddrphy_init(struct stm32mp1_ddrphy *phy, u32 pir);
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A D | stm32mp1_ddr_regs.h | 143 u32 pir; /* 0x04 R/W PHY Initialization*/ member
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/u-boot/arch/powerpc/cpu/mpc85xx/ |
A D | mp.c | 54 out_be32(&pic->pir, 1 << nr); in cpu_reset() 56 (void)in_be32(&pic->pir); in cpu_reset() 57 out_be32(&pic->pir, 0x0); in cpu_reset()
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/u-boot/arch/arm/mach-sunxi/ |
A D | dram_sun8i_a23.c | 233 writel(0x00000003, &mctl_phy->pir); in mctl_init() 241 writel(0x000005f3, &mctl_phy->pir); in mctl_init() 249 writel(0x5f3, &mctl_phy->pir); in mctl_init()
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A D | dram_sun6i.c | 161 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); in mctl_channel_init() 162 writel(MCTL_PIR_STEP1, &mctl_phy->pir); in mctl_channel_init() 192 setbits_le32(&mctl_phy->pir, MCTL_PIR_CLEAR_STATUS); in mctl_channel_init() 193 writel(MCTL_PIR_STEP2, &mctl_phy->pir); in mctl_channel_init()
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A D | dram_sunxi_dw.c | 26 writel(val | PIR_INIT, &mctl_ctl->pir); in mctl_phy_init() 317 writel(PIR_CLRSR, &mctl_ctl->pir); in mctl_h3_zq_calibration_quirk() 344 writel(PIR_CLRSR, &mctl_ctl->pir); in mctl_h3_zq_calibration_quirk() 350 writel(PIR_CLRSR, &mctl_ctl->pir); in mctl_h3_zq_calibration_quirk()
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A D | dram_sun9i.c | 752 clrsetbits_le32(&mctl_phy->pir, MCTL_PIR_MASK, 0x20df3); in mctl_channel_init() 754 clrsetbits_le32(&mctl_phy->pir, MCTL_PIR_MASK, 0x2c573); in mctl_channel_init() 759 while ((readl(&mctl_phy->pir) & MCTL_PIR_INIT) != MCTL_PIR_INIT) { in mctl_channel_init()
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A D | dram_sun8i_a33.c | 177 writel(val, &mctl_ctl->pir); in mctl_set_pir()
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A D | dram_sun50i_h6.c | 63 writel(val, &mctl_phy->pir); in mctl_phy_pir_init() 64 writel(val | BIT(0), &mctl_phy->pir); /* Start initialisation. */ in mctl_phy_pir_init()
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A D | dram_sun8i_a83t.c | 209 writel(val, &mctl_ctl->pir); in mctl_set_pir()
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/u-boot/drivers/ram/rockchip/ |
A D | sdram_rk3188.c | 163 setbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set() 172 clrbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set() 304 setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST in phy_init() 332 setbits_le32(&publ->pir, in memory_init() 440 setbits_le32(&publ->pir, PIR_CLRSR); in data_training() 443 setbits_le32(&publ->pir, in data_training()
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A D | sdram_rk3288.c | 163 setbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set() 172 clrbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set() 363 setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST in phy_init() 391 setbits_le32(&publ->pir, in memory_init() 499 setbits_le32(&publ->pir, PIR_CLRSR); in data_training() 502 setbits_le32(&publ->pir, in data_training()
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/u-boot/arch/arm/include/asm/arch-sunxi/ |
A D | dram_sun8i_a33.h | 70 u32 pir; /* 0x00 */ member
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A D | dram_sunxi_dw.h | 82 u32 pir; /* 0x00 PHY initialization register */ member
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A D | dram_sun8i_a83t.h | 70 u32 pir; /* 0x00 */ member
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A D | dram_sun9i.h | 98 u32 pir; /* 0x04 PHY initialisation register */ member
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A D | dram_sun50i_h6.h | 152 u32 pir; /* 0x004 */ member
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A D | dram_sun8i_a23.h | 164 u32 pir; /* 0x04 */ member
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A D | dram_sun6i.h | 162 u32 pir; /* 0x04 */ member
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/u-boot/arch/arm/include/asm/arch-rockchip/ |
A D | ddr_rk3288.h | 168 u32 pir; member
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/u-boot/drivers/spi/ |
A D | stm32_qspi.c | 39 u32 pir; /* 0x2C */ member
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/u-boot/arch/powerpc/include/asm/ |
A D | immap_86xx.h | 547 uint pir; /* 0x41090 - Processor Initialization Register */ member
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A D | immap_85xx.h | 648 u32 pir; /* Processor Initialization */ member
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