| /u-boot/arch/x86/lib/ |
| A D | pirq_routing.c | 17 static u8 pirq_get_next_free_irq(struct udevice *dev, u8 *pirq, u16 bitmap, in pirq_get_next_free_irq() argument
59 unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]; in pirq_route_irqs() local
63 memset(pirq, 0, CONFIG_MAX_PIRQ_LINKS); in pirq_route_irqs()
89 if (!pirq[link]) { in pirq_route_irqs()
90 irq = pirq_get_next_free_irq(dev, pirq, bitmap, in pirq_route_irqs()
92 pirq[link] = irq; in pirq_route_irqs()
94 irq = pirq[link]; in pirq_route_irqs()
111 debug("PIRQ%c: %d\n", 'A' + i, pirq[i]); in pirq_route_irqs()
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| A D | mpspec.c | 284 __weak int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) in mp_determine_pci_dstirq() argument
287 return pirq + 16; in mp_determine_pci_dstirq()
327 pr.pirq = fdt_addr_to_cpu(cell[2]); in mptable_add_intsrc()
340 dstirq = mp_determine_pci_dstirq(bus, dev, func, pr.pirq); in mptable_add_intsrc()
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| /u-boot/arch/x86/cpu/ |
| A D | irq.c | 83 u8 pirq; in pirq_check_irq_routed() local
87 pirq_linkno_to_reg(priv, link), &pirq); in pirq_check_irq_routed()
89 pirq = readb((uintptr_t)priv->ibase + in pirq_check_irq_routed()
92 pirq &= 0xf; in pirq_check_irq_routed()
95 if (pirq < 3 || pirq == 8 || pirq == 13) in pirq_check_irq_routed()
98 return pirq == irq ? true : false; in pirq_check_irq_routed()
140 int bus, int device, int pin, int pirq) in fill_irq_info() argument
275 pr.pirq = fdt_addr_to_cpu(cell[2]); in create_pirq_routing_table()
280 'A' + pr.pirq); in create_pirq_routing_table()
299 pirq_linkno_to_reg(priv, pr.pirq)) in create_pirq_routing_table()
[all …]
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| /u-boot/doc/device-tree-bindings/misc/ |
| A D | intel,irq-router.txt | 11 - intel,pirq-config : Specifies the IRQ routing register programming mechanism.
16 configuration space, required only if intel,pirq-config = "ibase".
22 - intel,pirq-link : Specifies the PIRQ link information with two cells. The
25 - intel,pirq-regmap : Specifies PIRQ routing register offset of all PIRQ links,
30 link, as specified by the first cell of intel,pirq-link.
31 - intel,pirq-mask : Specifies the IRQ mask representing the 16 IRQs in the
33 - intel,pirq-routing : Specifies all PCI devices' IRQ routing information,
48 intel,pirq-config = "pci";
49 intel,pirq-link = <0x60 8>;
50 intel,pirq-mask = <0xdef8>;
[all …]
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| A D | intel-lpc.txt | 20 - intel,pirq-routing : Speciffies the routing IRQ number for each of PIRQA-H,
51 intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
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| /u-boot/arch/x86/dts/ |
| A D | qemu-x86_i440fx.dts | 66 intel,pirq-config = "pci";
67 intel,pirq-link = <0x60 4>;
68 intel,pirq-mask = <0x0e40>;
69 intel,pirq-routing = <
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| A D | qemu-x86_q35.dts | 77 intel,pirq-config = "pci";
80 intel,pirq-link = <0x60 8>;
81 intel,pirq-mask = <0x0e40>;
82 intel,pirq-routing = <
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| A D | cougarcanyon2.dts | 109 intel,pirq-config = "pci";
112 intel,pirq-link = <0x60 8>;
113 intel,pirq-regmap = <
123 intel,pirq-mask = <0xcee0>;
124 intel,pirq-routing = <
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| A D | galileo.dts | 102 intel,pirq-config = "pci";
104 intel,pirq-link = <0x60 8>;
105 intel,pirq-mask = <0xdef8>;
106 intel,pirq-routing = <
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| A D | cherryhill.dts | 84 intel,pirq-config = "ibase";
86 intel,pirq-link = <8 8>;
87 intel,pirq-mask = <0xdee0>;
88 intel,pirq-routing = <
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| A D | crownbay.dts | 159 intel,pirq-config = "pci";
161 intel,pirq-link = <0x60 8>;
162 intel,pirq-mask = <0xcee0>;
163 intel,pirq-routing = <
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| A D | bayleybay.dts | 108 intel,pirq-config = "ibase";
111 intel,pirq-link = <8 8>;
112 intel,pirq-mask = <0xdee0>;
113 intel,pirq-routing = <
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| A D | baytrail_som-db5800-som-6867.dts | 132 intel,pirq-config = "ibase";
135 intel,pirq-link = <8 8>;
136 intel,pirq-mask = <0xdee0>;
137 intel,pirq-routing = <
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| A D | conga-qeval20-qa3-e3845.dts | 119 intel,pirq-config = "ibase";
122 intel,pirq-link = <8 8>;
123 intel,pirq-mask = <0xdee0>;
124 intel,pirq-routing = <
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| A D | dfi-bt700.dtsi | 130 intel,pirq-config = "ibase";
133 intel,pirq-link = <8 8>;
134 intel,pirq-mask = <0xdee0>;
135 intel,pirq-routing = <
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| A D | minnowmax.dts | 132 intel,pirq-config = "ibase";
135 intel,pirq-link = <8 8>;
136 intel,pirq-mask = <0xdee0>;
137 intel,pirq-routing = <
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| A D | chromebook_samus.dts | 145 gpio_pirq: gpio-pirq {
150 pirq-apic = <PIRQ_APIC_ROUTE>;
575 intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
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| A D | chromebook_link.dts | 416 intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
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| /u-boot/arch/x86/cpu/qemu/ |
| A D | qemu.c | 169 int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) in mp_determine_pci_dstirq() argument
186 irq = pirq < 8 ? pirq + 16 : pirq + 12; in mp_determine_pci_dstirq()
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| /u-boot/arch/x86/include/asm/ |
| A D | irq.h | 62 int pirq; member
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| A D | mpspec.h | 448 int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq);
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| /u-boot/include/xen/interface/ |
| A D | event_channel.h | 78 u32 pirq; member
149 u32 pirq; /* EVTCHNSTAT_pirq */ member
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| /u-boot/doc/device-tree-bindings/gpio/ |
| A D | intel,x86-broadwell-pinctrl.txt | 28 - pirq-apic - the pin will be routed to the IOxAPIC
103 gpio_pirq: gpio-pirq {
107 pirq-apic = <PIRQ_APIC_ROUTE>;
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| /u-boot/doc/arch/ |
| A D | x86.rst | 521 on the intel,pirq-routing property below.
525 intel,pirq-routing = <
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