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Searched refs:pitmg (Results 1 – 4 of 4) sorted by relevance

/u-boot/arch/arm/mach-sunxi/dram_timings/
A Dddr3_1333.c79 (wr_latency << 0), &mctl_ctl->pitmg[0]); in mctl_set_timing_params()
A Dlpddr3_stock.c75 (wr_latency << 0), &mctl_ctl->pitmg[0]); in mctl_set_timing_params()
A Dddr2_v3s.c76 (wr_latency << 0), &mctl_ctl->pitmg[0]); in mctl_set_timing_params()
/u-boot/arch/arm/include/asm/arch-sunxi/
A Ddram_sunxi_dw.h95 u32 pitmg[2]; /* 0x80 PHY interface timing registers */ member

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