Searched refs:plic (Results 1 – 9 of 9) sorted by relevance
| /u-boot/arch/riscv/lib/ |
| A D | andes_plic.c | 40 writel(en, (void __iomem *)ENABLE_REG(gd->arch.plic, hart)); in enable_ipi()
55 gd->arch.plic = base; in riscv_init_ipi()
90 writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic, in riscv_send_ipi()
100 source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
101 writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart)); in riscv_clear_ipi()
108 *pending = readl((void __iomem *)PENDING_REG(gd->arch.plic, in riscv_get_ipi()
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| /u-boot/arch/riscv/dts/ |
| A D | microchip-mpfs-icicle-kit.dts | 210 interrupt-parent = <&plic>;
233 interrupt-parent = <&plic>;
258 interrupt-parent = <&plic>;
275 interrupt-parent = <&plic>;
295 interrupt-parent = <&plic>;
306 interrupt-parent = <&plic>;
317 interrupt-parent = <&plic>;
328 interrupt-parent = <&plic>;
338 interrupt-parent = <&plic>;
372 interrupt-parent = <&plic>;
[all …]
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| A D | fu540-c000.dtsi | 144 compatible = "sifive,plic-1.0.0";
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| A D | k210.dtsi | 143 compatible = "kendryte,k210-plic", "riscv,plic0";
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| /u-boot/arch/riscv/include/asm/ |
| A D | global_data.h | 25 void __iomem *plic; /* plic base address */ member
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| /u-boot/doc/device-tree-bindings/pwm/ |
| A D | pwm-sifive.txt | 28 interrupt-parent = <&plic>;
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| /u-boot/doc/board/sipeed/ |
| A D | maix.rst | 182 …[ 0.000000] plic: interrupt-controller@C000000: mapped 65 interrupts with 2 handlers for 2 cont…
643 0x0C000000 0x4000000 plic
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| /u-boot/doc/board/microchip/ |
| A D | mpfs_icicle.rst | 334 [ 0.000000] plic: mapped 186 interrupts with 4 handlers for 9 contexts.
586 [ 0.000000] plic: mapped 53 interrupts with 4 handlers for 9 contexts.
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| /u-boot/doc/board/sifive/ |
| A D | fu540.rst | 306 [ 0.000000] plic: mapped 53 interrupts with 4 handlers for 9 contexts.
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