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Searched refs:pll (Results 1 – 25 of 203) sorted by relevance

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/u-boot/drivers/clk/imx/
A Dclk-pllv3.c50 u32 div = (readl(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_generic_get_rate()
69 val &= ~(pll->div_mask << pll->div_shift); in clk_pllv3_generic_set_rate()
86 if (pll->powerup_set) in clk_pllv3_generic_enable()
127 u32 div = readl(pll->base) & pll->div_mask; in clk_pllv3_sys_get_rate()
175 u32 div = readl(pll->base) & pll->div_mask; in clk_pllv3_av_get_rate()
259 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in imx_clk_pllv3()
260 if (!pll) in imx_clk_pllv3()
292 kfree(pll); in imx_clk_pllv3()
296 pll->base = base; in imx_clk_pllv3()
298 clk = &pll->clk; in imx_clk_pllv3()
[all …]
A Dclk-pll14xx.c178 tmp = readl(pll->base); in clk_pll1416x_set_rate()
180 writel(tmp, pll->base); in clk_pll1416x_set_rate()
184 writel(tmp, pll->base); in clk_pll1416x_set_rate()
188 writel(tmp, pll->base); in clk_pll1416x_set_rate()
205 writel(tmp, pll->base); in clk_pll1416x_set_rate()
214 writel(tmp, pll->base); in clk_pll1416x_set_rate()
338 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in imx_clk_pll14xx()
339 if (!pll) in imx_clk_pll14xx()
355 pll->base = base; in imx_clk_pll14xx()
360 clk = &pll->clk; in imx_clk_pll14xx()
[all …]
/u-boot/drivers/clk/at91/
A Dclk-sam9x60-pll.c113 pll->id); in sam9x60_frac_pll_set_rate()
151 pll->id); in sam9x60_frac_pll_get_rate()
171 pll->id); in sam9x60_frac_pll_enable()
230 pll->id); in sam9x60_frac_pll_disable()
261 pll->id); in sam9x60_div_pll_enable()
290 pll->id); in sam9x60_div_pll_disable()
320 pll->id); in sam9x60_div_pll_set_rate()
355 pll->id); in sam9x60_div_pll_get_rate()
385 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in sam9x60_clk_register_pll()
386 if (!pll) in sam9x60_clk_register_pll()
[all …]
/u-boot/drivers/clk/rockchip/
A Dclk_pll.c205 pll->mode_mask << pll->mode_shift, in rk3036_pll_set_rate()
212 rk_clrsetreg(base + pll->con_offset, in rk3036_pll_set_rate()
237 while (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) in rk3036_pll_set_rate()
240 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, in rk3036_pll_set_rate()
243 pll, readl(base + pll->con_offset), in rk3036_pll_set_rate()
259 shift = pll->mode_shift; in rk3036_pll_get_rate()
260 mask = pll->mode_mask << shift; in rk3036_pll_get_rate()
305 switch (pll->type) { in rockchip_pll_get_rate()
307 pll->mode_mask = PLL_MODE_MASK; in rockchip_pll_get_rate()
330 switch (pll->type) { in rockchip_pll_set_rate()
[all …]
/u-boot/arch/arm/mach-keystone/
A Dclock.c69 if (data->pll == MAIN_PLL) in configure_mult_div()
101 tmp = pllctl_reg_read(data->pll, secctl); in configure_main_pll()
131 offset = pllctl_reg(data->pll, div1) + i; in configure_main_pll()
207 if (data->pll == MAIN_PLL) in init_pll()
222 int pll; in init_plls() local
224 for (pll = MAIN_PLL; pll < MAX_PLL_COUNT; pll++) { in init_plls()
225 data = get_pll_init_data(pll); in init_plls()
280 static unsigned long pll_freq_get(int pll) in pll_freq_get() argument
286 if (pll == MAIN_PLL) { in pll_freq_get()
294 (pllctl_reg_read(pll, mult) & in pll_freq_get()
[all …]
A Dcmd_clock.c16 .pll = MAIN_PLL,
28 cmd_pll_data.pll = PASS_PLL; in do_pll_cmd()
31 cmd_pll_data.pll = TETRIS_PLL; in do_pll_cmd()
35 cmd_pll_data.pll = DDR3A_PLL; in do_pll_cmd()
37 cmd_pll_data.pll = DDR3B_PLL; in do_pll_cmd()
40 cmd_pll_data.pll = DDR3_PLL; in do_pll_cmd()
50 cmd_pll_data.pll, cmd_pll_data.pll_m, in do_pll_cmd()
/u-boot/arch/m68k/cpu/mcf5445x/
A Dspeed.c61 pll_t *pll = (pll_t *)MMAP_PLL; in clock_exit_limp() local
75 pll_t *pll = (pll_t *)MMAP_PLL; in setup_5441x_clocks() local
82 out_be32(&pll->pcr, 0x00000013); in setup_5441x_clocks()
94 temp = in_be32(&pll->pcr); in setup_5441x_clocks()
97 out_be32(&pll->pcr, temp); in setup_5441x_clocks()
99 temp = in_be32(&pll->pdr); in setup_5441x_clocks()
102 out_be32(&pll->pdr, temp); in setup_5441x_clocks()
114 pdr = in_be32(&pll->pdr); in setup_5441x_clocks()
134 pll_t *pll = (pll_t *)MMAP_PLL; in setup_5445x_clocks() local
179 out_be32(&pll->pcr, pcrvalue); in setup_5445x_clocks()
[all …]
/u-boot/drivers/clk/mediatek/
A Dclk-mtk.c105 ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS; in __mtk_pll_recalc_rate()
139 if (pll->pd_reg != pll->pcw_reg) { in mtk_pll_set_rate_regs()
145 val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift); in mtk_pll_set_rate_regs()
148 if (pll->pcw_chg_reg) { in mtk_pll_set_rate_regs()
173 unsigned long fmin = pll->fmin ? pll->fmin : 1000 * MHZ; in mtk_pll_calc_values()
178 if (freq > pll->fmax) in mtk_pll_calc_values()
179 freq = pll->fmax; in mtk_pll_calc_values()
188 ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS; in mtk_pll_calc_values()
213 postdiv = (readl(priv->base + pll->pd_reg) >> pll->pd_shift) & in mtk_apmixedsys_get_rate()
217 pcw = readl(priv->base + pll->pcw_reg) >> pll->pcw_shift; in mtk_apmixedsys_get_rate()
[all …]
/u-boot/drivers/clk/kendryte/
A Dpll.c450 reg = readl(pll->reg); in k210_pll_set_rate()
459 writel(reg, pll->reg); in k210_pll_set_rate()
496 u32 mask = GENMASK(pll->width - 1, 0) << pll->shift; in k210_pll_waitfor_lock()
583 struct k210_pll *pll; in k210_register_pll() local
585 pll = kzalloc(sizeof(*pll), GFP_KERNEL); in k210_register_pll()
586 if (!pll) in k210_register_pll()
588 pll->reg = reg; in k210_register_pll()
589 pll->lock = lock; in k210_register_pll()
590 pll->shift = shift; in k210_register_pll()
591 pll->width = width; in k210_register_pll()
[all …]
/u-boot/arch/arm/cpu/arm926ejs/mx27/
A Dgeneric.c30 unsigned int mfi = (pll >> 10) & 0xf; in imx_decode_pll()
31 unsigned int mfn = pll & 0x3ff; in imx_decode_pll()
32 unsigned int mfd = (pll >> 16) & 0x3ff; in imx_decode_pll()
33 unsigned int pd = (pll >> 26) & 0xf; in imx_decode_pll()
50 if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) { in clk_in_26m()
61 ulong cscr = readl(&pll->cscr); in imx_get_mpllclk()
75 ulong cscr = readl(&pll->cscr); in imx_get_armclk()
90 ulong cscr = readl(&pll->cscr); in imx_get_ahbclk()
102 ulong cscr = readl(&pll->cscr); in imx_get_spllclk()
186 writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1); in cpu_eth_init()
[all …]
/u-boot/arch/arm/mach-keystone/include/mach/
A Dclock_defs.h56 #define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg)) argument
57 #define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg)) argument
58 #define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg)) argument
60 #define pllctl_reg_rmw(pll, reg, mask, val) \ argument
61 pllctl_reg_write(pll, reg, \
62 (pllctl_reg_read(pll, reg) & ~(mask)) | val)
64 #define pllctl_reg_setbits(pll, reg, mask) \ argument
65 pllctl_reg_rmw(pll, reg, 0, mask)
67 #define pllctl_reg_clrbits(pll, reg, mask) \ argument
68 pllctl_reg_rmw(pll, reg, mask, 0)
/u-boot/arch/m68k/cpu/mcf5227x/
A Dspeed.c59 pll_t *pll = (pll_t *)MMAP_PLL; in clock_exit_limp() local
65 while (!(in_be32(&pll->psr) & PLL_PSR_LOCK)) in clock_exit_limp()
76 pll_t *pll = (pll_t *)MMAP_PLL; in get_clocks() local
80 pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF; in get_clocks()
92 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; in get_clocks()
95 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF); in get_clocks()
97 out_be32(&pll->pcr, pcrvalue); in get_clocks()
99 ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * in get_clocks()
105 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; in get_clocks()
114 temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1; in get_clocks()
[all …]
/u-boot/arch/m68k/cpu/mcf52x2/
A Dspeed.c24 pll_t *pll = (pll_t *) MMAP_PLL; in get_clocks() local
26 out_8(&pll->odr, CONFIG_SYS_PLL_ODR); in get_clocks()
27 out_8(&pll->fdr, CONFIG_SYS_PLL_FDR); in get_clocks()
60 pll_t *pll = (pll_t *)(MMAP_PLL); in get_clocks() local
63 out_be32(&pll->syncr, 0x01080000); in get_clocks()
64 while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK)) in get_clocks()
66 out_be32(&pll->syncr, 0x01000000); in get_clocks()
67 while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK)) in get_clocks()
/u-boot/arch/arm/include/asm/arch-s32v234/
A Dmc_cgm_regs.h70 #define PLLDIG_PLLDV(pll) ((MC_CGM0_BASE_ADDR + 0x00000028) + ((pll) * 0x80)) argument
94 #define PLLDIG_PLLFD(pll) ((MC_CGM0_BASE_ADDR + 0x00000030) + ((pll) * 0x80)) argument
100 #define PLLDIG_PLLCAL1(pll) ((MC_CGM0_BASE_ADDR + 0x00000038) + ((pll) * 0x80)) argument
110 #define DFS_DLLPRG1(pll) (DFS0_BASE_ADDR + 0x00000000 + ((pll) * 0x80)) argument
137 #define DFS_CTRL(pll) (DFS0_BASE_ADDR + 0x00000018 + ((pll) * 0x80)) argument
142 #define DFS_PORTSR(pll) (DFS0_BASE_ADDR + 0x0000000C +((pll) * 0x80)) argument
144 #define DFS_PORTRESET(pll) (DFS0_BASE_ADDR + 0x00000014 + ((pll) * 0x80)) argument
151 #define DFS_DVPORTn(pll,n) (DFS0_BASE_ADDR + ((pll) * 0x80) + (0x0000001C + ((n) * 0x4))) argument
/u-boot/board/freescale/s32v234evb/
A Dclock.c39 switch (pll) { in select_pll_source_clk()
50 pll_idx = pll; in select_pll_source_clk()
103 if (select_pll_source_clk(pll, refclk_freq) < 0) { in program_pll()
117 PLLDIG_PLLFD_SMDEN, PLLDIG_PLLFD(pll)); in program_pll()
126 if ((pll == ARM_PLL) || (pll == ENET_PLL) || (pll == DDR_PLL)) { in program_pll()
128 writel(DFS_CTRL_DLL_RESET, DFS_CTRL(pll)); in program_pll()
140 DFS_DVPORTn(pll, i)); in program_pll()
145 writel(readl(DFS_CTRL(pll)) & ~DFS_CTRL_DLL_RESET, in program_pll()
146 DFS_CTRL(pll)); in program_pll()
147 writel(readl(DFS_PORTRESET(pll)) & in program_pll()
[all …]
/u-boot/arch/mips/mach-ath79/qca953x/
A Dclk.c36 u32 val, ctrl, xtal, pll, div; in get_clocks() local
48 pll = xtal / div; in get_clocks()
53 pll *= div; in get_clocks()
58 pll >>= div; in get_clocks()
63 gd->cpu_clk = pll / div; in get_clocks()
70 pll = xtal / div; in get_clocks()
75 pll *= div; in get_clocks()
80 pll >>= div; in get_clocks()
85 gd->mem_clk = pll / div; in get_clocks()
/u-boot/arch/m68k/cpu/mcf532x/
A Dspeed.c55 pll_t *pll = (pll_t *)(MMAP_PLL); in get_sys_clock() local
69 u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1; in get_sys_clock()
76 return (FREF * in_8(&pll->pfdr)) / (BUSDIV * 4); in get_sys_clock()
146 pll_t *pll = (pll_t *)(MMAP_PLL); in clock_pll() local
156 mfd = (in_be32(&pll->pcr) & 0x3F) + 1; in clock_pll()
161 mfd = in_8(&pll->pfdr); in clock_pll()
213 out_be32(&pll->pdr, in clock_pll()
219 clrbits_be32(&pll->pcr, ~PLL_PCR_FBDIV_UNMASK); in clock_pll()
220 setbits_be32(&pll->pcr, PLL_PCR_FBDIV(mfd - 1)); in clock_pll()
224 out_8(&pll->podr, in clock_pll()
[all …]
/u-boot/arch/arm/mach-uniphier/clk/
A DMakefile14 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += pll-ld4.o dpll-tail.o
15 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o pll-pro4.o dpll-tail.o
16 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += pll-ld4.o dpll-tail.o
20 obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o pll-base-ld20.o pll-ld11.o
21 obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o pll-base-ld20.o pll-ld20.o
22 obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += clk-pxs3.o pll-base-ld20.o pll-pxs3.o
/u-boot/arch/mips/mach-ath79/ar933x/
A Dclk.c36 u32 val, xtal, pll, div; in get_clocks() local
46 pll = xtal / div; in get_clocks()
51 pll *= div; in get_clocks()
56 pll >>= div; in get_clocks()
63 gd->cpu_clk = pll / div; in get_clocks()
68 gd->mem_clk = pll / div; in get_clocks()
73 gd->bus_clk = pll / div; in get_clocks()
/u-boot/drivers/video/sunxi/
A Dsunxi_dw_hdmi.c35 u32 pll; member
98 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_init()
102 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_init()
106 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_init()
152 writel(0x30dc5fc0, &phy->pll); in sunxi_dw_hdmi_phy_set()
170 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_set()
178 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_set()
184 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_set()
192 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_set()
198 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_set()
[all …]
/u-boot/arch/arm/cpu/armv7/iproc-common/
A Darmpll.c41 uint32_t pll; in armpll_config() local
96 pll = readl(IHOST_PROC_CLK_PLLARMB); in armpll_config()
97 pll &= ~((1 << IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_WIDTH) - 1); in armpll_config()
102 pll |= ndiv_frac; in armpll_config()
103 writel(pll, IHOST_PROC_CLK_PLLARMB); in armpll_config()
125 pll = readl(IHOST_PROC_CLK_PLLARMA); in armpll_config()
126 pll |= (1 << IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_POST_RESETB); in armpll_config()
127 writel(pll, IHOST_PROC_CLK_PLLARMA); in armpll_config()
/u-boot/arch/arm/mach-tegra/
A Dclock.c104 data = readl(&pll->pll_base); in clock_ll_read_pll()
108 data = readl(&pll->pll_misc); in clock_ll_read_pll()
119 struct clk_pll *pll = NULL; in clock_start_pll() local
125 pll = get_pll(clkid); in clock_start_pll()
141 if (pll) in clock_start_pll()
154 if (pll) { in clock_start_pll()
538 struct clk_pll *pll; in clock_get_rate() local
550 pll = get_pll(clkid); in clock_get_rate()
551 if (!pll) in clock_get_rate()
595 struct clk_pll *pll; in clock_set_rate() local
[all …]
/u-boot/arch/m68k/cpu/mcf523x/
A Dspeed.c25 pll_t *pll = (pll_t *)(MMAP_PLL); in get_clocks() local
27 out_be32(&pll->syncr, PLL_SYNCR_MFD(1)); in get_clocks()
29 while (!(in_be32(&pll->synsr) & PLL_SYNSR_LOCK)) in get_clocks()
/u-boot/arch/arm/mach-imx/mx5/
A Dclock.c168 ctrl = readl(&pll->ctrl); in decode_pll()
173 op = readl(&pll->hfs_op); in decode_pll()
175 mfn = readl(&pll->mfn); in decode_pll()
176 mfd = readl(&pll->mfd); in decode_pll()
177 op = readl(&pll->op); in decode_pll()
609 pll->pd = (u32)pd; in calc_pll_params()
610 pll->mfi = (u32)mfi; in calc_pll_params()
612 pll->mfn = (u32)mfn; in calc_pll_params()
614 pll->mfd = (u32)mfd; in calc_pll_params()
635 &pll->op); \
[all …]
/u-boot/arch/arm/dts/
A Dstm32mp157c-odyssey-som-u-boot.dtsi101 pll2: st,pll@1 {
102 compatible = "st,stm32mp1-pll";
110 pll3: st,pll@2 {
111 compatible = "st,stm32mp1-pll";
119 pll4: st,pll@3 {
120 compatible = "st,stm32mp1-pll";

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