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Searched refs:pll11_cfg (Results 1 – 3 of 3) sorted by relevance

/u-boot/arch/arm/mach-sunxi/
A Dclock_sun6i.c294 CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg); in clock_set_pll11()
296 while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD) in clock_set_pll11()
A Ddram_sunxi_dw.c430 clrbits_le32(&ccm->pll11_cfg, CCM_PLL11_CTRL_EN); in mctl_sys_init()
/u-boot/arch/arm/include/asm/arch-sunxi/
A Dclock_sun6i.h33 u32 pll11_cfg; /* 0x4c pll11 (ddr1) control (A33 only) */ member

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