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Searched refs:pll1_mult (Results 1 – 4 of 4) sorted by relevance

/u-boot/drivers/clk/renesas/
A Drcar-gen2-cpg.h31 unsigned int pll1_mult; member
A Drcar-gen3-cpg.h64 u8 pll1_mult; member
A Dclk-rcar-gen2.c165 rate = (gen2_clk_get_rate(&parent) * pll_config->pll1_mult) / 2; in gen2_clk_get_rate()
168 core->parent, pll_config->pll1_mult, rate); in gen2_clk_get_rate()
A Dclk-rcar-gen3.c223 rate = gen3_clk_get_rate64(&parent) * pll_config->pll1_mult; in gen3_clk_get_rate64()
227 core->parent, pll_config->pll1_mult, in gen3_clk_get_rate64()

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